doc/simh.doc

{\rtf1\adeflang1025\ansi\ansicpg1252\uc1\adeff0\deff0\stshfdbch31505\stshfloch31506\stshfhich31506\stshfbi0\deflang1033\deflangfe1033\themelang1033\themelangfe0\themelangcs0{\fonttbl{\f0\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f1\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604020202020204}Arial;}
{\f2\fbidi \fmodern\fcharset0\fprq1{\*\panose 02070309020205020404}Courier New;}{\f3\fbidi \froman\fcharset2\fprq2{\*\panose 05050102010706020507}Symbol;}{\f10\fbidi \fnil\fcharset2\fprq2{\*\panose 05000000000000000000}Wingdings;}
{\f11\fbidi \fmodern\fcharset128\fprq1{\*\panose 02020609040205080304}MS Mincho{\*\falt MS ??};}{\f34\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria Math;}{\f37\fbidi \fswiss\fcharset0\fprq2{\*\panose 020f0502020204030204}Calibri;}
{\f38\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604030504040204}Tahoma;}{\f39\fbidi \fmodern\fcharset128\fprq1{\*\panose 00000000000000000000}@MS Mincho;}{\flomajor\f31500\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}
{\fdbmajor\f31501\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\fhimajor\f31502\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria;}
{\fbimajor\f31503\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\flominor\f31504\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}
{\fdbminor\f31505\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\fhiminor\f31506\fbidi \fswiss\fcharset0\fprq2{\*\panose 020f0502020204030204}Calibri;}
{\fbiminor\f31507\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f40\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\f41\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
{\f43\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\f44\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\f45\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\f46\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
{\f47\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\f48\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\f50\fbidi \fswiss\fcharset238\fprq2 Arial CE;}{\f51\fbidi \fswiss\fcharset204\fprq2 Arial Cyr;}
{\f53\fbidi \fswiss\fcharset161\fprq2 Arial Greek;}{\f54\fbidi \fswiss\fcharset162\fprq2 Arial Tur;}{\f55\fbidi \fswiss\fcharset177\fprq2 Arial (Hebrew);}{\f56\fbidi \fswiss\fcharset178\fprq2 Arial (Arabic);}
{\f57\fbidi \fswiss\fcharset186\fprq2 Arial Baltic;}{\f58\fbidi \fswiss\fcharset163\fprq2 Arial (Vietnamese);}{\f60\fbidi \fmodern\fcharset238\fprq1 Courier New CE;}{\f61\fbidi \fmodern\fcharset204\fprq1 Courier New Cyr;}
{\f63\fbidi \fmodern\fcharset161\fprq1 Courier New Greek;}{\f64\fbidi \fmodern\fcharset162\fprq1 Courier New Tur;}{\f65\fbidi \fmodern\fcharset177\fprq1 Courier New (Hebrew);}{\f66\fbidi \fmodern\fcharset178\fprq1 Courier New (Arabic);}
{\f67\fbidi \fmodern\fcharset186\fprq1 Courier New Baltic;}{\f68\fbidi \fmodern\fcharset163\fprq1 Courier New (Vietnamese);}{\f152\fbidi \fmodern\fcharset0\fprq1 MS Mincho Western{\*\falt MS ??};}
{\f150\fbidi \fmodern\fcharset238\fprq1 MS Mincho CE{\*\falt MS ??};}{\f151\fbidi \fmodern\fcharset204\fprq1 MS Mincho Cyr{\*\falt MS ??};}{\f153\fbidi \fmodern\fcharset161\fprq1 MS Mincho Greek{\*\falt MS ??};}
{\f154\fbidi \fmodern\fcharset162\fprq1 MS Mincho Tur{\*\falt MS ??};}{\f157\fbidi \fmodern\fcharset186\fprq1 MS Mincho Baltic{\*\falt MS ??};}{\f380\fbidi \froman\fcharset238\fprq2 Cambria Math CE;}
{\f381\fbidi \froman\fcharset204\fprq2 Cambria Math Cyr;}{\f383\fbidi \froman\fcharset161\fprq2 Cambria Math Greek;}{\f384\fbidi \froman\fcharset162\fprq2 Cambria Math Tur;}{\f387\fbidi \froman\fcharset186\fprq2 Cambria Math Baltic;}
{\f388\fbidi \froman\fcharset163\fprq2 Cambria Math (Vietnamese);}{\f410\fbidi \fswiss\fcharset238\fprq2 Calibri CE;}{\f411\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}{\f413\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;}
{\f414\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;}{\f417\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}{\f418\fbidi \fswiss\fcharset163\fprq2 Calibri (Vietnamese);}{\f420\fbidi \fswiss\fcharset238\fprq2 Tahoma CE;}
{\f421\fbidi \fswiss\fcharset204\fprq2 Tahoma Cyr;}{\f423\fbidi \fswiss\fcharset161\fprq2 Tahoma Greek;}{\f424\fbidi \fswiss\fcharset162\fprq2 Tahoma Tur;}{\f425\fbidi \fswiss\fcharset177\fprq2 Tahoma (Hebrew);}
{\f426\fbidi \fswiss\fcharset178\fprq2 Tahoma (Arabic);}{\f427\fbidi \fswiss\fcharset186\fprq2 Tahoma Baltic;}{\f428\fbidi \fswiss\fcharset163\fprq2 Tahoma (Vietnamese);}{\f429\fbidi \fswiss\fcharset222\fprq2 Tahoma (Thai);}
{\f432\fbidi \fmodern\fcharset0\fprq1 @MS Mincho Western;}{\f430\fbidi \fmodern\fcharset238\fprq1 @MS Mincho CE;}{\f431\fbidi \fmodern\fcharset204\fprq1 @MS Mincho Cyr;}{\f433\fbidi \fmodern\fcharset161\fprq1 @MS Mincho Greek;}
{\f434\fbidi \fmodern\fcharset162\fprq1 @MS Mincho Tur;}{\f437\fbidi \fmodern\fcharset186\fprq1 @MS Mincho Baltic;}{\flomajor\f31508\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}
{\flomajor\f31509\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\flomajor\f31511\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\flomajor\f31512\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}
{\flomajor\f31513\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\flomajor\f31514\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\flomajor\f31515\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}
{\flomajor\f31516\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fdbmajor\f31518\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fdbmajor\f31519\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
{\fdbmajor\f31521\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fdbmajor\f31522\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\fdbmajor\f31523\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}
{\fdbmajor\f31524\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fdbmajor\f31525\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fdbmajor\f31526\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}
{\fhimajor\f31528\fbidi \froman\fcharset238\fprq2 Cambria CE;}{\fhimajor\f31529\fbidi \froman\fcharset204\fprq2 Cambria Cyr;}{\fhimajor\f31531\fbidi \froman\fcharset161\fprq2 Cambria Greek;}{\fhimajor\f31532\fbidi \froman\fcharset162\fprq2 Cambria Tur;}
{\fhimajor\f31535\fbidi \froman\fcharset186\fprq2 Cambria Baltic;}{\fhimajor\f31536\fbidi \froman\fcharset163\fprq2 Cambria (Vietnamese);}{\fbimajor\f31538\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}
{\fbimajor\f31539\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fbimajor\f31541\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fbimajor\f31542\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}
{\fbimajor\f31543\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fbimajor\f31544\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbimajor\f31545\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}
{\fbimajor\f31546\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\flominor\f31548\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\flominor\f31549\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
{\flominor\f31551\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\flominor\f31552\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\flominor\f31553\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}
{\flominor\f31554\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\flominor\f31555\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\flominor\f31556\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}
{\fdbminor\f31558\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fdbminor\f31559\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fdbminor\f31561\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}
{\fdbminor\f31562\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\fdbminor\f31563\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fdbminor\f31564\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
{\fdbminor\f31565\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fdbminor\f31566\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fhiminor\f31568\fbidi \fswiss\fcharset238\fprq2 Calibri CE;}
{\fhiminor\f31569\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}{\fhiminor\f31571\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;}{\fhiminor\f31572\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;}
{\fhiminor\f31575\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}{\fhiminor\f31576\fbidi \fswiss\fcharset163\fprq2 Calibri (Vietnamese);}{\fbiminor\f31578\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}
{\fbiminor\f31579\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fbiminor\f31581\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fbiminor\f31582\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}
{\fbiminor\f31583\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fbiminor\f31584\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbiminor\f31585\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}
{\fbiminor\f31586\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}}{\colortbl;\red0\green0\blue0;\red0\green0\blue255;\red0\green255\blue255;\red0\green255\blue0;\red255\green0\blue255;\red255\green0\blue0;\red255\green255\blue0;
\red255\green255\blue255;\red0\green0\blue128;\red0\green128\blue128;\red0\green128\blue0;\red128\green0\blue128;\red128\green0\blue0;\red128\green128\blue0;\red128\green128\blue128;\red192\green192\blue192;\red163\green21\blue21;}{\*\defchp 
\fs22\loch\af31506\hich\af31506\dbch\af31505 }{\*\defpap \ql \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 }\noqfpromote {\stylesheet{
\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \snext0 \sqformat \spriority0 Normal;}{
\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 
\b\fs28\lang1033\langfe1033\kerning28\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \slink15 \sqformat heading 1;}{\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \slink16 \sqformat heading 2;}{\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 
\fs24\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \slink17 \sqformat heading 3;}{\*\cs10 \additive Default Paragraph Font;}{\*
\ts11\tsrowd\trftsWidthB3\trpaddl108\trpaddr108\trpaddfl3\trpaddft3\trpaddfb3\trpaddfr3\tblind0\tblindtype3\tsvertalt\tsbrdrt\tsbrdrl\tsbrdrb\tsbrdrr\tsbrdrdgl\tsbrdrdgr\tsbrdrh\tsbrdrv \ql \li0\ri0\sa200\sl276\slmult1
\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\loch\f31506\hich\af31506\dbch\af31505\cgrid\langnp1033\langfenp1033 \snext11 \ssemihidden \sunhideused 
Normal Table;}{\*\cs15 \additive \rtlch\fcs1 \ab\af0\afs32 \ltrch\fcs0 \b\fs32\kerning32\loch\f31502\hich\af31502\dbch\af31501 \sbasedon10 \slink1 \slocked \spriority9 Heading 1 Char;}{\*\cs16 \additive \rtlch\fcs1 \ab\ai\af0\afs28 \ltrch\fcs0 
\b\i\fs28\loch\f31502\hich\af31502\dbch\af31501 \sbasedon10 \slink2 \slocked \ssemihidden \spriority9 Heading 2 Char;}{\*\cs17 \additive \rtlch\fcs1 \ab\af0\afs26 \ltrch\fcs0 \b\fs26\loch\f31502\hich\af31502\dbch\af31501 
\sbasedon10 \slink3 \slocked \ssemihidden \spriority9 Heading 3 Char;}{\*\cs18 \additive \rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b \sbasedon10 \sqformat Strong;}{\s19\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 
\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\fs20\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext19 \slink20 Body Text;}{\*\cs20 \additive \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f0\fs20 
\sbasedon10 \slink19 \slocked \ssemihidden Body Text Char;}{\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 
\fs20\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext21 \slink22 Body Text 2;}{\*\cs22 \additive \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f0\fs20 \sbasedon10 \slink21 \slocked \ssemihidden Body Text 2 Char;}{
\s23\ql \li0\ri0\sb120\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \sautoupd \spriority39 toc 1;}{\s24\ql \li200\ri0\sb120\widctlpar\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd \spriority39 toc 2;}{\s25\ql \li400\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 
\ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd \spriority39 toc 3;}{\s26\ql \li600\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin600\itap0 \rtlch\fcs1 
\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 4;}{\s27\ql \li800\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin800\itap0 \rtlch\fcs1 
\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 5;}{\s28\ql \li1000\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1000\itap0 \rtlch\fcs1 
\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 6;}{\s29\ql \li1200\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1200\itap0 \rtlch\fcs1 
\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 7;}{\s30\ql \li1400\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1400\itap0 \rtlch\fcs1 
\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 8;}{\s31\ql \li1600\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1600\itap0 \rtlch\fcs1 
\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 9;}{\s32\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \cbpat9 \rtlch\fcs1 
\af38\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f38\hich\af38\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext32 \slink33 Document Map;}{\*\cs33 \additive \rtlch\fcs1 \af38\afs16 \ltrch\fcs0 \f38\fs16 
\sbasedon10 \slink32 \slocked \ssemihidden Document Map Char;}{\s34\ql \li390\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 
\fs20\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext34 \slink35 Body Text Indent 2;}{\*\cs35 \additive \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f0\fs20 \sbasedon10 \slink34 \slocked \ssemihidden 
Body Text Indent 2 Char;}{\s36\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af2\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f2\hich\af2\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext36 \slink37 Plain Text;}{\*\cs37 \additive \rtlch\fcs1 \af2\afs20 \ltrch\fcs0 \f2\fs20 \sbasedon10 \slink36 \slocked \ssemihidden Plain Text Char;}{\s38\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 
\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext38 \sqformat \spriority34 \styrsid10051909 List Paragraph;}{
\s39\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af38\afs16\alang1025 \ltrch\fcs0 \fs16\lang1033\langfe1033\loch\f38\hich\af38\dbch\af31505\cgrid\langnp1033\langfenp1033 
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\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\loch\af1\hich\af1\dbch\af11\insrsid4550150 \hich\af1\dbch\af11\loch\f1 COPYRIGHT NOTICE
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \loch\af1\hich\af1\dbch\af11\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \loch\af1\hich\af1\dbch\af11\insrsid4550150 \hich\af1\dbch\af11\loch\f1 The following copyright notice applies to the SIMH source, binary, and documentation:
\par 
\par }\pard \ltrpar\s36\ql \li720\ri962\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin962\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \loch\af1\hich\af1\dbch\af11\insrsid4550150 \hich\af1\dbch\af11\loch\f1 
Original code published in 1993-2008, written by Robert M Supnik
\par \hich\af1\dbch\af11\loch\f1 Copyright (c) 1993-2008, Robert M Supnik
\par 
\par \hich\af1\dbch\af11\loch\f1 Permission is hereby grante\hich\af1\dbch\af11\loch\f1 
d, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, 
\hich\af1\dbch\af11\loch\f1 s\hich\af1\dbch\af11\loch\f1 ublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
\par 
\par \hich\af1\dbch\af11\loch\f1 The above copyright notice and this permission notice shall be included in all copies or substantial port\hich\af1\dbch\af11\loch\f1 ions of the Software.
\par 
\par \hich\af1\dbch\af11\loch\f1 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL ROBERT M SUP
\hich\af1\dbch\af11\loch\f1 NIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\par \hich\af1\dbch\af11\loch\f1 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE  SOFTWARE.
\par 
\par \hich\af1\dbch\af11\loch\f1 Except as contained in this notice, the na\hich\af1\dbch\af11\loch\f1 
me of Robert M Supnik shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik.
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Overview\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355607 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600300037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 4}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 2.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 
\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Data Types\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355608 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600300038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 4}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 
\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
VM Organization\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355609 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600300039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 5}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1}{
\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 CPU Organization\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 
PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355610 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Time Base
\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355611 
\\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Step Function\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355612 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Memory Organization\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355613 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 7}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Interrupt Organization\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355614 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 7}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1.5}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
I/O Dispatching\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355615 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 8}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1.6}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Instruction Execution\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355616 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 8}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.2}{
\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 P\hich\af0\dbch\af31505\loch\f0 eripheral Device Organization\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355617 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 9}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 
\b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.2.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Device Timing\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355618 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 10}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.2.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Clock Calibration\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355619 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 11}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.2.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Idling
\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355620 
\\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 11}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.2.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Data I/O
\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355621 
\\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 12}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 
\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.}{
\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Data Structures\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355622 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 
\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320032000000}}}{\fldrslt {\rtlch\fcs1 \af0 
\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 13}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 
\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1}{
\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 sim_device Structure\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 
PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355623 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 13}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Awidth and Aincr\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355624 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Device Flags\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355625 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Context
\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355626 
\\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Exa
\hich\af0\dbch\af31505\loch\f0 mine and Deposit Routines\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  
\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355627 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.5}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Reset Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355628 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 16}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.6}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Boot Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355629 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 16}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.7}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Attach and Detach Routines\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355630 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 16}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.8}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Memory Size Change Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _\hich\af0\dbch\af31505\loch\f0 Toc356355631 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 17}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.9}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Debug Controls\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355632 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 17}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.10}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Device Specific Help support\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355633 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 18}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.11}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Help Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355634 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 18}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.12}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Attach Help Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355635 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 19}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.2}{
\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 sim_unit Structure\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 
PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355636 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 19}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.2.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Unit Flags
\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355637 
\\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.2.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Service Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355638 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.3}{
\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 sim_reg Structure\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 
PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355639 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.3.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Register Flags\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355640 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 22}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4}{
\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 s\hich\af0\dbch\af31505\loch\f0 im_mtab Structure\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  
\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355641 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 22}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Validation Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355642 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Display Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 
_Toc356355643 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Help Flags
\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355644 
\\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Example arguments in the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 mstring}{\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  
\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc3563556\hich\af0\dbch\af31505\loch\f0 45 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4.5}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Help field
\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355646 
\\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.5}{
\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Other Data Structures\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 
PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355647 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 
\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 5.}{
\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 VM Provided Routines\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355648 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 
\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340038000000}}}{\fldrslt {\rtlch\fcs1 \af0 
\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 
\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 5.1}{
\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Instruction Execution\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 
PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355649 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 5.2}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 
\b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Binary Load and Dump\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355650 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 26}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 5.3}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 
\b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Symbolic Examination and Deposit\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355651 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 26}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 5.4}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 
\b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Optional Interfaces\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355652 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 27}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 5.4.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Once Only Initialization Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355653 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 27}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 5.4.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Address Input and Display\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _To\hich\af0\dbch\af31505\loch\f0 c356355654 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 27}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 5.4.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Command Input and Post-Processing\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355655 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 27}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 5.4.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 
\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
VM-Specific Commands\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355656 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 28}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 
\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 6.}{
\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Other SCP Facilities\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 
\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355657 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 
\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350037000000}}}{\fldrslt {\rtlch\fcs1 \af0 
\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 28}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 
\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 6.1}{
\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Terminal Input/Output Formatting Library\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  
\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355658 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 28}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 6.2}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 
\b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Terminal Multiplexer Emulation Library\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355659 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 29}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 6.3}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 
\b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Magnetic Tape Emulation Library\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355660 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600360030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 34}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 6.4}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 
\b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Disk Emulation Library\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355661 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600360031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 35}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 6.5}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 
\b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 
Breakpoint Support\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0  \hich\af0\dbch\af31505\loch\f0 PAGEREF 
\hich\af0\dbch\af31505\loch\f0 _Toc356355662 \\h\hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600360032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\hich\af0\dbch\af31505\loch\f0 37}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 
\deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 1.}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 
\b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Overview\tab \hich\af0\dbch\af31505\loch\f0 4}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 2.}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 
\b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Data Types\tab \hich\af0\dbch\af31505\loch\f0 4}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 
\b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 VM Organization\tab \hich\af0\dbch\af31505\loch\f0 5}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 CPU Organization\tab \hich\af0\dbch\af31505\loch\f0 6}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Time Base\tab \hich\af0\dbch\af31505\loch\f0 6}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Step Function\tab \hich\af0\dbch\af31505\loch\f0 6}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.3}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Memory Organization\tab \hich\af0\dbch\af31505\loch\f0 7}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.4}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Interrupt Organization\tab \hich\af0\dbch\af31505\loch\f0 7}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.5}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 I/O Dispatching\tab \hich\af0\dbch\af31505\loch\f0 8}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.6}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Instruction Execution\tab \hich\af0\dbch\af31505\loch\f0 8}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Peripheral Device Organization\tab \hich\af0\dbch\af31505\loch\f0 9}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Device Timing\tab \hich\af0\dbch\af31505\loch\f0 10}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Clock Calibration\tab \hich\af0\dbch\af31505\loch\f0 11}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.3}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Idling\tab \hich\af0\dbch\af31505\loch\f0 11}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.4}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Data I/O\tab \hich\af0\dbch\af31505\loch\f0 12}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 
\b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Data Structures\tab \hich\af0\dbch\af31505\loch\f0 13}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 sim_device Structure\tab \hich\af0\dbch\af31505\loch\f0 13}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Awidth and Aincr\tab \hich\af0\dbch\af31505\loch\f0 15}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Device Flags\tab \hich\af0\dbch\af31505\loch\f0 15}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.3}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Context\tab \hich\af0\dbch\af31505\loch\f0 15}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.4}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Examine and Deposit Routines\tab \hich\af0\dbch\af31505\loch\f0 15}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.5}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Reset Routine\tab \hich\af0\dbch\af31505\loch\f0 16}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.6}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Boot Routine\tab \hich\af0\dbch\af31505\loch\f0 16}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.7}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Attach and Detach Routines\tab \hich\af0\dbch\af31505\loch\f0 16}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.8}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Memory Size Change Routine\tab \hich\af0\dbch\af31505\loch\f0 17}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.9}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Debug Controls\tab \hich\af0\dbch\af31505\loch\f0 17}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.10}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Device Specific Help support\tab \hich\af0\dbch\af31505\loch\f0 18}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.11}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Help Routine\tab \hich\af0\dbch\af31505\loch\f0 18}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.12}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Attach Help Routine\tab \hich\af0\dbch\af31505\loch\f0 19}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.2}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 sim_unit Structure\tab \hich\af0\dbch\af31505\loch\f0 19}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.2.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Unit Flags\tab \hich\af0\dbch\af31505\loch\f0 20}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.2.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Service Routine\tab \hich\af0\dbch\af31505\loch\f0 20}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.3}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 sim_reg Structure\tab \hich\af0\dbch\af31505\loch\f0 20}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.3.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Register Flags\tab \hich\af0\dbch\af31505\loch\f0 22}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 sim_mtab Structure\tab \hich\af0\dbch\af31505\loch\f0 22}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Validation Routine\tab \hich\af0\dbch\af31505\loch\f0 24}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Display Routine\tab \hich\af0\dbch\af31505\loch\f0 24}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.3}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Help Flags\tab \hich\af0\dbch\af31505\loch\f0 24}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.4}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Example arguments in the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 mstring}{
\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab \hich\af0\dbch\af31505\loch\f0 25}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.5}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Help field\tab \hich\af0\dbch\af31505\loch\f0 25}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.5}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Other Data Structures\tab \hich\af0\dbch\af31505\loch\f0 25}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 
\b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 VM Provided Routines\tab \hich\af0\dbch\af31505\loch\f0 25}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.1}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Instruction Execution\tab \hich\af0\dbch\af31505\loch\f0 25}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.2}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Binary Load and Dump\tab \hich\af0\dbch\af31505\loch\f0 26}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.3}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Symbolic Examination and Deposit\tab \hich\af0\dbch\af31505\loch\f0 26}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Optional Interfaces\tab \hich\af0\dbch\af31505\loch\f0 27}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Once Only Initialization Routine\tab \hich\af0\dbch\af31505\loch\f0 27}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 

\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Address Input and Display\tab \hich\af0\dbch\af31505\loch\f0 27}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4.3}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Command Input and Post-Processing\tab \hich\af0\dbch\af31505\loch\f0 27}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 

\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4.4}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 
\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 VM-Specific Commands\tab \hich\af0\dbch\af31505\loch\f0 28}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 
\b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Other SCP Facilities\tab \hich\af0\dbch\af31505\loch\f0 28}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.1}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Terminal Input/Output Formatting Library\tab \hich\af0\dbch\af31505\loch\f0 28}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 

\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.2}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Terminal Multiplexer Emulation Library\tab \hich\af0\dbch\af31505\loch\f0 29}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 

\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.3}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Magnetic Tape Emulation Library\tab \hich\af0\dbch\af31505\loch\f0 34}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.4}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Disk Emulation Library\tab \hich\af0\dbch\af31505\loch\f0 35}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.5}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 
\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\hich\af0\dbch\af31505\loch\f0 Breakpoint Support\tab \hich\af0\dbch\af31505\loch\f0 37}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 
\par }}}\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sectd \ltrsect
\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \page 
\par {\*\bkmkstart _Toc356355607}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Overview{\*\bkmkend _Toc356355607}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 
SIMH (history simulators) is a set of portable programs, written in C, which simulate various historically interesting computers.  This document describes how to design, write, and check out a new simulator for SIMH.  It is not an introducti
\hich\af1\dbch\af31505\loch\f1 
on to either the philosophy or external operation of SIMH, and the reader should be familiar with both of those topics before proceeding.  Nor is it a guide to the internal design or operation of SIMH, except insofar as those areas interact with simulator
\hich\af1\dbch\af31505\loch\f1  \hich\af1\dbch\af31505\loch\f1 
design.  Instead, this manual presents and explains the form, meaning, and operation of the interfaces between simulators and the SIMH simulator control package.  It also offers some suggestions for utilizing the services SIMH offers and explains the cons
\hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 raints that all simulators operating within SIMH will experience.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Some terminology: Each simulator consists of a standard }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 simulator control package}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  (SCP and related libraries), which provides a control framework and utility routines for a simulator; and a\hich\af1\dbch\af31505\loch\f1  unique }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 virtual machine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (VM), which implements the simulated processor and selected peripherals.  A VM consists of multiple }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 devices}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
, such as the CPU, paper tape reader, disk controller, etc.  Each controller consists of a named state space (called }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 register\hich\af1\dbch\af31505\loch\f1 s}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ) and one or more }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 units}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .  Each unit consists of a numbered state space (called a }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 data set}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ). }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 host computer}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is the system on which SIMH runs; the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 target computer}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is the system being simulated.
\par 
\par \hich\af1\dbch\af31505\loch\f1 SIMH is unabashedly based on the MIMIC simulation system, \hich\af1\dbch\af31505\loch\f1 designed in the late 1960\hich\f1 \rquote \loch\f1 s by Len Fehskens, Mike McCarthy, and Bob Supnik.   This document is based on MIMIC
\hich\f1 \rquote \loch\f1 \hich\f1 s published interface specification, \'93\loch\f1 \hich\f1 How to Write a Virtual Machine for the MIMIC Simulation System\'94\loch\f1 , by Len Fehskens and Bob Supnik.
\par 
\par {\*\bkmkstart _Toc356355608}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Types{\*\bkmkend _Toc356355608}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 
SIMH is written in C.  The host system must support (at least) 32-bit data types (64-bit data types for the PDP-10 and other large-word target systems).  To cope with the vagaries of C data types, SIMH defines some unambiguou
\hich\af1\dbch\af31505\loch\f1 s data types for its interfaces:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 SIMH data type\tab \tab \tab interpretation in typical 32-bit C
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 int8, uint8\tab \tab \tab signed char, unsigned char
\par \tab \hich\af1\dbch\af31505\loch\f1 int16, uint16\tab \tab \tab signed short, unsigned short
\par \tab \hich\af1\dbch\af31505\loch\f1 int32, uint32\tab \tab \tab signed int, unsigned int
\par \tab \hich\af1\dbch\af31505\loch\f1 t_int64, t_uint64\tab \tab \tab long long, _int64\hich\af1\dbch\af31505\loch\f1  (system specific)
\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab \tab \tab simulated address, uint32 or t_uint64
\par \tab \hich\af1\dbch\af31505\loch\f1 t_value\tab \tab \tab \tab simulated value, uint32 or t_uint64
\par \tab \hich\af1\dbch\af31505\loch\f1 t_svalue\tab \tab \tab simulated signed value, int32 or t_int64
\par \tab \hich\af1\dbch\af31505\loch\f1 t_mtrec\tab \tab \tab \tab mag tape record length, uint32
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab \tab \tab status code, int
\par \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab \tab \tab true/\hich\af1\dbch\af31505\loch\f1 false value, int
\par 
\par \hich\af1\dbch\af31505\loch\f1 [The inconsistency in naming t_int64 and t_uint64 is due to Microsoft VC++, which uses int64 as a structure name member in the master Windows definitions file.]
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 In addition, SIMH defines structures for each of its major data elements:

\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEVICE}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 device definition structure
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 unit definition structure
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 register definition structure
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 modifier definition structure
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 command definition structure
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEBTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 debug table entry structure
\par 
\par {\*\bkmkstart _Toc356355609}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Organizatio\hich\af1\dbch\af31505\loch\f1 n{\*\bkmkend _Toc356355609}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 A virtual machine (VM) is a collection of devices bound together through their internal logic.  Each device is named and corresponds more or less to a hunk of hardware on the real machine; for example:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 VM device\tab \tab \tab Real machine hardware
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 CPU\tab \tab \tab \tab central processor and main memory
\par \tab \hich\af1\dbch\af31505\loch\f1 PTR\tab \tab \tab \tab paper tape reader controller and paper tape reader
\par \tab \hich\af1\dbch\af31505\loch\f1 TTI\tab \tab \tab \tab console keyboard
\par \tab \hich\af1\dbch\af31505\loch\f1 TTO\tab \tab \tab \tab console output
\par \tab \hich\af1\dbch\af31505\loch\f1 DKP\tab \tab \tab \tab disk pack controller and drives
\par 
\par \hich\af1\dbch\af31505\loch\f1 There may be more than one device per physical hardware entity, as \hich\af1\dbch\af31505\loch\f1 
for the console; but for each user-accessible device there must be at least one.  One of these devices will have the pre-eminent responsibility for directing simulated operations.  Normally, this is the CPU, but it could be a higher-level entity, such as 
\hich\af1\dbch\af31505\loch\f1 a\hich\af1\dbch\af31505\loch\f1  bus master.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The VM actually runs as a subroutine of the simulator control package (SCP).  It provides a master routine for running simulated programs and other routines and data structures to implement SCP\hich\f1 \rquote \loch\f1 
s command and control functions.  The interfaces\hich\af1\dbch\af31505\loch\f1  between a VM and SCP are relatively few:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 Interface\tab \tab \tab Function
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_name[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 simulator name string

\par \tab \hich\af1\dbch\af31505\loch\f1 REG *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_pc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 
pointer to simulated program counter
\par \tab \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 
maximum number of words in an instruction
\par \tab \hich\af1\dbch\af31505\loch\f1 DEVICE *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 
table of pointers to simulated devices, NULL terminated
\par \tab \hich\af1\dbch\af31505\loch\f1 char *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_messages[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 
table of pointers to error messages
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1  (\'85\loch\f1 )\tab \tab 
binary loader subroutine
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_inst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (void)\tab \tab 
instruction execution subroutine
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1  (\'85\loch\f1 )\tab \tab 
\hich\af1\dbch\af31505\loch\f1 symbolic instruction parse subroutine
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1  (\'85\loch\f1 )\tab \tab 
symbolic instruction print subroutine
\par 
\par \hich\af1\dbch\af31505\loch\f1 In addition, there are six optional interfaces, which can be used for special situations, such as GUI implementations:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 Interface\tab \tab \tab \tab Function
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim\hich\af1\dbch\af31505\loch\f1 _vm_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
) (void)\tab \tab pointer to once-only initialization routine for VM
\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )
\tab pointer to address parsing routine
\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )
\tab pointer to address output routine
\par \tab \hich\af1\dbch\af31505\loch\f1 char (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 *sim_vm_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )\tab 
\tab pointer to command input ro\hich\af1\dbch\af31505\loch\f1 utine
\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_post}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )\tab 
\tab pointer to command post-processing routine
\par \tab \hich\af1\dbch\af31505\loch\f1 CTAB }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 *sim_vm_cmd}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 
pointer to simulator-specific command table
\par 
\par \hich\af1\dbch\af31505\loch\f1 There is no required organization for VM code.  The following convention has been used so far.  Let name be the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  of the real system (i1401 for the IBM 1401; i1620 for the IBM 1620; pdp1 for the PDP-1; pdp18b for the other 18-bit PDP\hich\f1 \rquote \loch\f1 
s; pdp8 for the PDP-8; pdp11 for the PDP-11; nova for Nova; hp2100 for the HP 21XX; h316 for the Honeywell 315/516; gri for the GRI-90\hich\af1\dbch\af31505\loch\f1 9\hich\af1\dbch\af31505\loch\f1 
; pdp10 for the PDP-10; vax for the VAX; sds for the SDS-940):
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .h contains definitions for the particular simulator
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 _sys.c contains all the SCP interfaces except the instruction simulator
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 _cpu.c contains the instruction simulator and \hich\af1\dbch\af31505\loch\f1 CPU data structures
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 _stddev.c contains the peripherals which were standard with the real system.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 _lp.c contains the line printer.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 _mt.c contains the mag tape controller and drives, etc.
\par }\pard \ltrpar\ql \fi1440\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The SIMH standard definitions are in sim_defs.h.  The base components of SIMH are:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 Source module\tab \tab header file\tab \tab module
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 scp.c\tab \tab \tab scp.h\tab \tab \tab control package
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_console.c\tab \tab sim_console.h\tab \tab terminal I/O library
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_fio.c\tab \tab sim_fio.h\tab \tab file I/O library
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_timer\hich\af1\dbch\af31505\loch\f1 .c\tab \tab sim_timer.h\tab \tab timer library
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_sock.c\tab \tab sim_sock.h\tab \tab socket I/O library
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_ether.c\tab \tab sim_ether.h\tab \tab Ethernet I/O library
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 sim_serial.c\tab \tab sim_serial.h\tab \tab Serial Port I/O library

\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 sim_tmxr.c\tab \tab sim_tmxr.h\tab \tab terminal multiplexer simulation library
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 sim_disk.c\tab \tab si\hich\af1\dbch\af31505\loch\f1 m_disk.h\tab \tab 
disk simulation library
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 sim_tape.c\tab \tab sim_tape.h\tab \tab magtape simulation library
\par {\*\bkmkstart _Toc356355610}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CPU Organization{\*\bkmkend _Toc356355610}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Most CPU\hich\f1 \rquote \loch\f1 s perform at least the following functions:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Time keeping
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction fetching
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Address decoding
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Execu\hich\af1\dbch\af31505\loch\f1 tion of non-I/O instructions
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 I/O command processing
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Interrupt processing
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Instruction execution is actually the least complicated part of the design; memory and I/O organization should be tackled first.
\par {\*\bkmkstart _Toc356355611}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Time Base{\*\bkmkend _Toc356355611}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 
In order to simulate asynchronous events, such as I/O completion, the VM must define and keep a time base.  This can be accurate (for example, nanoseconds of execution) or arbitrary (for example, number of instructions executed), but it must be used consi
\hich\af1\dbch\af31505\loch\f1 s\hich\af1\dbch\af31505\loch\f1 tently throughout the VM.  All existing VM\hich\f1 \rquote \loch\f1 s count time in instructions.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The CPU is responsible for counting down the event counter }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  and calling the asynchronous event controller }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .  SCP does the record keeping for timing.
\par {\*\bkmkstart _Toc356355612}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Step Function{\*\bkmkend _Toc356355612}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP implements a stepping function using the step command.  STEP counts down a specified number of time units (as described in section 3.1.1) and then stops simulation.  The VM can override the STEP command\hich\f1 \rquote 
\loch\f1 s coun\hich\af1\dbch\af31505\loch\f1 ts by calling routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_cancel_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :

\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls25\adjustright\rin0\lin720\itap0 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat sim_cancel_step (void) \hich\f1 \endash \loch\f1  cancel STEP count down.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The VM can then inspect variable }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 to see if a STEP command is in progress.  If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is non-zero, it represents the number of steps to execute.  T\hich\af1\dbch\af31505\loch\f1 he VM can count down }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  using its own counting method, such as cycles, instructions, or memory references.
\par {\*\bkmkstart _Toc356355613}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Organization{\*\bkmkend _Toc356355613}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The criterion for memory layout is very simple: use the SIMH data type that is as large as\hich\af1\dbch\af31505\loch\f1 
 (or if necessary, larger than), the word length of the real machine.  Note that the criterion is word length, not addressability: the PDP-11 has byte addressable memory, but it is a 16-bit machine, and its memory is defined as uint16 M[].  It may seem te
\hich\af1\dbch\af31505\loch\f1 m\hich\af1\dbch\af31505\loch\f1 
pting to define memory as a union of int8 and int16 data types, but this would make the resulting VM endian-dependent.  Instead, the VM should be based on the underlying word size of the real machine, and byte manipulation should be done explicitly.  Exam
\hich\af1\dbch\af31505\loch\f1 p\hich\af1\dbch\af31505\loch\f1 les:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 Simulator\tab \tab memory size\tab \tab memory declaration
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 IBM 1620\tab \tab 5-bit\tab \tab \tab uint8
\par \tab \hich\af1\dbch\af31505\loch\f1 IBM 1401\tab \tab 7-bit\tab \tab \tab uint8
\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-8\tab \tab \tab 12-bit\tab \tab \tab uint16
\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-11, Nova\tab \tab 16-bit\tab \tab \tab uint16
\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-1\tab \tab \tab 18-bit\tab \tab \tab uint32
\par \tab \hich\af1\dbch\af31505\loch\f1 VAX\tab \tab \tab 32-bit\tab \tab \tab uint32
\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-10, IBM 7094\tab 36-bit\tab \tab \tab t_uint64
\par {\*\bkmkstart _Toc356355614}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Interrupt Organization{\*\bkmkend _Toc356355614}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The design of the VM\hich\f1 \rquote \loch\f1 s interrupt structure is a complex interaction between efficiency and fidelity to the hardware.  If the VM\hich\f1 \rquote \loch\f1 
s interrupt structure is too abstract, interrupt driven software may not run.  On the o\hich\af1\dbch\af31505\loch\f1 
ther hand, if it follows the hardware too literally, it may significantly reduce simulation speed.  One rule I can offer is to minimize the fetch-phase cost of interrupts, even if this complicates the (much less frequent) evaluation of the interrupt syste
\hich\af1\dbch\af31505\loch\f1 m\hich\af1\dbch\af31505\loch\f1 
 following an I/O operation or asynchronous event.  Another is not to over-generalize; even if the real hardware could support 64 or 256 interrupting devices, the simulators will be running much smaller configurations.  I\hich\f1 \rquote \loch\f1 
ll start with a simple interrupt \hich\af1\dbch\af31505\loch\f1 s\hich\af1\dbch\af31505\loch\f1 tructure and then offer suggestions for generalization.
\par 
\par \hich\af1\dbch\af31505\loch\f1 In the simplest structure, interrupt requests correspond to device flags and are kept in\hich\af1\dbch\af31505\loch\f1 
 an interrupt request variable, with one flag per bit.  The fetch-phase evaluation of interrupts consists of two steps: are interrupts enabled, and is there an interrupt outstanding?  If all the interrupt requests are kept as single-bit flags in a variabl
\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 , the fetch-phase test is very fast:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 if (int_enable && int_requests) \{\hich\f1  \'85\loch\f1 \hich\f1 process interrupt\'85\loch\f1  \}
\par 
\par \hich\af1\dbch\af31505\loch\f1 Indeed, the interrupt enable flag can be made the highest bit in the interrupt request variable, and the two tests combined:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 if (int_requests > INT_ENABLE) \{ \loch\af1\dbch\af31505\hich\f1 \'85\loch\f1 \hich\f1 process interrupt\'85\loch\f1  \}
\par 
\par \hich\af1\dbch\af31505\loch\f1 Setting or clearing device flags directly sets or clears the appropriate interrupt request flag:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 set: \tab int_requests = int_requests | DEVICE_FLAG;
\par \tab \hich\af1\dbch\af31505\loch\f1 clear:\tab int_requests = int_requests & ~DEVICE_FLAG;
\par 
\par \hich\af1\dbch\af31505\loch\f1 At a slightly higher complexity,\hich\af1\dbch\af31505\loch\f1 
 interrupt requests do not correspond directly to device flags but are based on masking the device flags with an enable (or disable) mask.  There are now two parallel variables: device flags and interrupt enable mask.  The fetch-phase test is now:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 If (in\hich\af1\dbch\af31505\loch\f1 t_enable && (dev_flags & int_enables)) \{\hich\f1  \'85\loch\f1 \hich\f1 process interrupt\'85\loch\f1  \}
\par 
\par \hich\af1\dbch\af31505\loch\f1 As a next step, the VM may keep a summary interrupt request variable, which is updated by any change to a device flag or interrupt enable/disable:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 enable:\tab int_requests = device_flags & int_e\hich\af1\dbch\af31505\loch\f1 nables;
\par \tab \hich\af1\dbch\af31505\loch\f1 disable:\tab int_requests = device_flags & ~int_disables;
\par 
\par \hich\af1\dbch\af31505\loch\f1 This simplifies the fetch phase test slightly.
\par 
\par \hich\af1\dbch\af31505\loch\f1 At yet higher complexity, the interrupt system may be too complex or too large to evaluate during the fetch-phase.  In this case, an interrupt p\hich\af1\dbch\af31505\loch\f1 
ending flag is created, and it is evaluated by subroutine call whenever a change could occur (start of execution, I/O instruction issued, device time out occurs).  This makes fetch-phase evaluation simple and isolates interrupt evaluation to a common subr
\hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 utine.
\par 
\par \hich\af1\dbch\af31505\loch\f1 
If required for interrupt processing, the highest priority interrupting device can be determined by scanning the interrupt request variable from high priority to low until a set bit is found.  The bit position can then be back-mapped through a tabl
\hich\af1\dbch\af31505\loch\f1 e to determine the address or interrupt vector of the interrupting device.
\par {\*\bkmkstart _Toc356355615}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 I/O Dispatching{\*\bkmkend _Toc356355615}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 I/O dispatching consists of four steps:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Identify the I/O command and analyze for the device address.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Locate th\hich\af1\dbch\af31505\loch\f1 e selected device.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Break down the I/O command into standard fields.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Call the device processor.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Analyzing an I/O command is usually easy.  Most systems have one or more explicit I/O instructions containing an I/O command and a device address.  Memory\hich\af1\dbch\af31505\loch\f1 
 mapped I/O is more complicated; the identification of a reference to I/O space becomes part of memory addressing.  This usually requires centralizing memory reads and writes into subroutines, rather than as inline code.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Once an I/O command has been analy\hich\af1\dbch\af31505\loch\f1 
zed, the CPU must locate the device subroutine.  The simplest way is a large switch statement with hardwired subroutine calls. More modular is to call through a dispatch table, with NULL entries representing non-existent devices; this also simplifies supp
\hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 
rt for modifiable device addresses and configurable devices.  Before calling the device routine, the CPU usually breaks down the I/O command into standard fields.  This simplifies writing the peripheral simulator.
\par {\*\bkmkstart _Toc356355616}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.6\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution{\*\bkmkend _Toc356355616}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Instruction execution is the responsibility of VM subroutine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .  It is called from SCP as a result of a RUN, GO, CONT, or BOOT command.  It begins executing instructions at the current PC (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_PC}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to its register description bloc\hich\af1\dbch\af31505\loch\f1 k) and continues until halted by an error or an external event.
\par 
\par \hich\af1\dbch\af31505\loch\f1 When called, the CPU needs to account for any state changes that the user made.  For example, it may need to re-evaluate whether an interrupt is pending, or restore frequently used state to l\hich\af1\dbch\af31505\loch\f1 
ocal register variables for efficiency.  The actual instruction fetch and execute cycle is usually structured as a loop controlled by an error variable, e.g.,
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 reason = 0;
\par \tab \hich\af1\dbch\af31505\loch\f1 do \{\hich\f1  \'85\loch\f1  \} while (reason == 0);\tab or\tab while (reason == 0) \{\hich\f1  \'85\loch\f1  \}
\par 
\par \hich\af1\dbch\af31505\loch\f1 Within this loop, the \hich\af1\dbch\af31505\loch\f1 usual order of events is:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If the event timer }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  has reached zero, process any timed events.  This is done by SCP subroutine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Because this is the polling mechanism for user-generated processor halts (^E), errors must be reco
\hich\af1\dbch\af31505\loch\f1 gnized immediately:
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li1440\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 if (sim_interval <= 0) \{
\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
if (reason = sim_process_event ()) break;  \}
\par }\pard \ltrpar\ql \fi2160\li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Check for outstanding interrupts and process if required.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Check for other processor-unique events, such as wait-state outstanding or traps outstanding.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Check for an instruction breakpoint.  SCP has a comprehensive breakpoint facility.  It allows a VM to define many different kinds of breakpoints.  The VM checks for execution (type E) breakpoints during instruction fetch.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Fetch the next instruction, in\hich\af1\dbch\af31505\loch\f1 
crement the PC, optionally decode the address, and dispatch (via a switch statement) for execution.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 A few guidelines for implementation:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls5\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls5\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
In general, code should reflect the hardware being simulated.  This is usually simplest and easiest to debug.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls5\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls5\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The VM should provide some debugging aids.  The existing CPU\hich\f1 
\rquote \loch\f1 s all provide multiple instruction breakpoints, a PC change queue, error stops on invalid instructions or operations, and symbolic examination and modification of memory.
\par {\*\bkmkstart _Toc356355617}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Periphe\hich\af1\dbch\af31505\loch\f1 ral Device Organization{\*\bkmkend _Toc356355617}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The basic elements of a VM are devices, each corresponding roughly to a real chunk of hardware.  A device consists of register-based state and one or more units.  Thus, a multi-drive disk subsystem is a single device (
\hich\af1\dbch\af31505\loch\f1 
representing the hardware of the real controller) and one or more units (each representing a single disk drive).  Sometimes the device and its unit are the same entity as, for example, in the case of a paper tape reader.  However, a single physical device
,\hich\af1\dbch\af31505\loch\f1  such as the console, may be broken up for convenience into separate input and output devices.
\par 
\par \hich\af1\dbch\af31505\loch\f1 In general, units correspond to individual sources of input or output (one tape transport, one A-to-D channel).  Units are the basic medium for both device timi\hich\af1\dbch\af31505\loch\f1 
ng and device I/O.  Except for the console, all I/O devices are simulated as host-resident files.  SCP allows the user to make an explicit association between a host-resident file and a simulated hardware entity.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Both devices and units have state.  Device\hich\af1\dbch\af31505\loch\f1 s operate on }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 registers}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , which contain information about the state of the device, and indirectly, about the state of the units.  Units operate on }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 data sets}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , which may be thought of as individual instances of input or output, such as a disk pack or a punched\hich\af1\dbch\af31505\loch\f1 
 paper tape.  In a typical multi-unit device, all units are the same, and the device performs similar operations on all of them, depending on which one has been selected by the program being simulated.
\par 
\par \hich\af1\dbch\af31505\loch\f1 (Note: SIMH, like MIMIC, restricts registers to devic\hich\af1\dbch\af31505\loch\f1 es. Replicated registers, for example, disk drive current state, are handled via register arrays.)
\par 
\par \hich\af1\dbch\af31505\loch\f1 For each structural level, SIMH defines, and the VM must supply, a corresponding data structure.  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_device}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structures correspond to devices, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  struc\hich\af1\dbch\af31505\loch\f1 tures to registers, and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  structures to units.  These structures are described in detail in section 4.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The primary functions of a peripheral are:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls6\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls6\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 command decoding and execution
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls6\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls6\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 device timing
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls6\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls6\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 data transmission.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 
Command decoding is fairly obvious.  At least one section of the peripheral code module will be devoted to processing directives issued by the CPU.  Typically, the command decoder will be responsible for register and flag manipulation, and for issuing or 
\hich\af1\dbch\af31505\loch\f1 c\hich\af1\dbch\af31505\loch\f1 anceling I/O requests.  The former is easy, but the later requires a thorough understanding of device timing.
\par {\*\bkmkstart _Toc356355618}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Timing{\*\bkmkend _Toc356355618}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The principal problem in I/O device simulation is imitating asynchronous operations in a sequential\hich\af1\dbch\af31505\loch\f1 
 simulation environment.  Fortunately, the timing characteristics of most I/O devices do not vary with external circumstances.  The distinction between devices whose timing is externally generated (e.g., console keyboard) and those whose timing is }{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1049593 \hich\af1\dbch\af31505\loch\f1 internal\hich\af1\dbch\af31505\loch\f1 ly}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 generated (disk, paper tape reader) is crucial.  With an externally timed device, there is no way to know when an in-progress operation will begin or end; with an internally timed device, given the time when an operation starts, the end time can be calc
\hich\af1\dbch\af31505\loch\f1 ulated.
\par 
\par \hich\af1\dbch\af31505\loch\f1 For an internally timed device, the elapsed time between the start and conclusion of an operation is called the wait time.  Some typical internally timed devices and their wait times include:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 PTR (300 char/sec)\tab \tab 3.3 msec
\par \tab \hich\af1\dbch\af31505\loch\f1 PTP (50 char/sec)\tab \tab 20 m\hich\af1\dbch\af31505\loch\f1 sec
\par \tab \hich\af1\dbch\af31505\loch\f1 CLK (line frequency)\tab \tab 16.6 msec
\par \tab \hich\af1\dbch\af31505\loch\f1 TTO (30 char/sec)\tab \tab 33 msec
\par 
\par \hich\af1\dbch\af31505\loch\f1 Mass storage devices, such as disks and tapes, do not have a fixed response time, but a start-to-finish time can be calculated based on current versus desired position, state of motion, etc.
\par 
\par \hich\af1\dbch\af31505\loch\f1 For an externally timed device, there is no portable mechanism by which a VM can be notified of an external event (for example, a key stroke).  Accordingly, all current VM\hich\f1 \rquote \loch\f1 
s poll for keyboard input, thus converting the externally timed keyboard to a pseu\hich\af1\dbch\af31505\loch\f1 
do-internally timed device.  A more general restriction is that SIMH is single-threaded.  Threaded operations must be done by polling using the unit timing mechanism, either with real units or fake units created expressly for polling.
\par 
\par \hich\af1\dbch\af31505\loch\f1 SCP provides the sup\hich\af1\dbch\af31505\loch\f1 
porting routines for device timing.  SCP maintains a list of devices (called active devices) that are in the process of timing out.  It also provides routines for querying or manipulating this list (called the active queue).  Lastly, it provides a routine
\hich\af1\dbch\af31505\loch\f1  \hich\af1\dbch\af31505\loch\f1 for checking for timed-out units and executing a VM-specified action when a time-out occurs.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Device timing is done with the UNIT structure, described in section 4.  To set up a timed operation, the peripheral calculates a waiting period for a unit and pla\hich\af1\dbch\af31505\loch\f1 
ces that unit on the active queue.  The CPU counts down the waiting period.  When the waiting period has expired, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  removes the unit from the active queue and calls a device subroutine.  A device may also cancel an outstanding timed operati\hich\af1\dbch\af31505\loch\f1 
on and query the state of the queue.  The timing subroutines are:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_activate}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, int32 wait).  This routine places the specified unit on the active queue with the specified waiting period.  A waiting period of 0 is legal; negative wai\hich\af1\dbch\af31505\loch\f1 
ts cause an error.  If the unit is already active, the active queue is not changed, and no error occurs.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_cancel}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr).  This routine removes the specified unit from the active queue.  If the unit is not on the queue, no error occurs.

\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_is_active}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr).  This routine tests whether a unit is in the active queue.  If it is, the routine returns }{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 TRUE(1)}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ; if it is not, the routine returns }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909 
\hich\af1\dbch\af31505\loch\f1 FALSE(}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 0}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 )}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0\pararsid13897431 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid10051909 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0\pararsid13897431 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 sim_activate_time}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr).  This routine returns the time the device has remaining in the queue + 1.  if it is not pending, the routine returns 0.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909\charrsid10051909 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 double }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_gtime}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (void).  This routine returns the time elapsed since the last RUN or BOOT command.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uint32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_gr\hich\af1\dbch\af31505\loch\f1 time}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (void).  This routine returns the low-order 32b of the time elapsed since the last RUN or BOOT command.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_qcount}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (void).  This routine returns the number of entries on the clock queue.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (void).  This routine rem\hich\af1\dbch\af31505\loch\f1 
oves all timed out units from the active queue and calls the appropriate device subroutine to service the time-out.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  This variable counts down the first outstanding timed event.  If there are no timed events outstanding, SCP counts 
\hich\af1\dbch\af31505\loch\f1 \hich\f1 down a \'93\loch\f1 \hich\f1 null interval\'94\loch\f1  of 10,000 time units.
\par {\*\bkmkstart _Toc356355619}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Clock Calibration{\*\bkmkend _Toc356355619}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The timing mechanism described in the previous section is approximate.  Devices, such as real-time clocks, which track wall time will be inaccurate.  SCP provid\hich\af1\dbch\af31505\loch\f1 
es routines to synchronize multiple simulated clocks (to a maximum of 8) to wall time.
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls15\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls15\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_rtcn_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 clock_interval, int32 clk).  This routine initializes the clock calibration mechanism for simulated clock }{\rtlch\fcs1 
\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 clk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The argument is returned a\hich\af1\dbch\af31505\loch\f1 s the result.
\par }\pard \ltrpar\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls15\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls15\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_rtcn_calb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 tickspersecond, int32 clk).  This routine calibrates simulated clock }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 clk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The argument is the number of clock ticks expected per second.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The VM must call }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_rtcn_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 for each simulated clock in two places: i\hich\af1\dbch\af31505\loch\f1 n the prolog of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 , before instruction execution starts, and whenever the real-time clock is started.  The simulator calls }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_rtcn_calb}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to calculate the actual interval delay when the real-time clock is serviced:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 /* clock start */
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 if (!sim_is_a\hich\af1\dbch\af31505\loch\f1 ctive (&clk_unit)) sim_activate (&clk_unit, sim_rtcn_init (clk_delay, clkno));
\par \tab \hich\af1\dbch\af31505\loch\f1 etc.
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 /* clock service */
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_activate (&clk_unit, sim_rtcb_calb (clk_ticks_per_second, clkno);
\par 
\par \hich\af1\dbch\af31505\loch\f1 The real-time clock is usually simulated clock 0; other clocks are used for \hich\af1\dbch\af31505\loch\f1 polling asynchronous multiplexers or intervals timers.
\par {\*\bkmkstart _Toc356355620}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Idling{\*\bkmkend _Toc356355620}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If a VM implements a free-running, calibrated clock of 100Hz or less, then the VM can also implement idling.  Idling is a way of pausing simulation when no real \hich\af1\dbch\af31505\loch\f1 
work is happening, without losing clock calibration.  The VM must detect when it is idle; it can then inform the host of this situation by calling }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls26\adjustright\rin0\lin720\itap0 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  (int32 clk, t_bool one_tick) \hich\f1 \endash \loch\f1  attempt to idle the VM until the next scheduled I\hich\af1\dbch\af31505\loch\f1 /O event, using simulated clock }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 clk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  as the time base, and decrement }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  by an appropriate number of cycles.  If a calibrated timer is not available, or the time until the next event is less than 1ms, decrement }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  by 1 if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 one_tick}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is TRUE\hich\af1\dbch\af31505\loch\f1 ; otherwise, leave sim_interval unchanged.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  returns TRUE if the VM actually idled, FALSE if it did not.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Because idling and throttling are mutually exclusive, the VM must inform SCP when idling is turned on or off:
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls26\adjustright\rin0\lin720\itap0 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_set_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  (UNIT *up\hich\af1\dbch\af31505\loch\f1 tr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  informs SCP that idling is enabled.
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 t_stat}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 sim_clr_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  informs SCP that idling is disabled.
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
sim_show_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1  displays whether idling is enabled or disabled, as seen by SCP.

\par {\*\bkmkstart _Toc356355621}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data I/O{\*\bkmkend _Toc356355621}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 For most devices, timing is half the battle (for clocks it is the entire war); the other half is I/O.  Some devices are simulated on real hardware (f\hich\af1\dbch\af31505\loch\f1 
or example, Ethernet controllers).  Most I/O devices are simulated as files on the host file system in little-endian format.  SCP provides facilities for associating files with units (ATTACH command) and for reading and writing data from and to devices in
\hich\af1\dbch\af31505\loch\f1  \hich\af1\dbch\af31505\loch\f1 a endian- and size-independent way.
\par 
\par \hich\af1\dbch\af31505\loch\f1 For most devices, the VM designer does not have to be concerned about the formatting of simulated device files.  I/O occurs in 1, 2, 4, or 8 byte quantities; SCP automatically chooses the correct data size and corrects 
\hich\af1\dbch\af31505\loch\f1 for byte ordering.  Specific issues:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Line printers should write data as 7-bit ASCII, with newlines replacing carriage-return/line-feed sequences.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Disks should be viewed as linear data sets, from sector 0 of surface 0 of cylinder 0 to the last sector on the disk.  This allows easy transcription of real disks to files usable by the simulator.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Magtapes, by convention, use a record based format.  Ea
\hich\af1\dbch\af31505\loch\f1 ch record consists of a leading 32-bit record length, the record data (padded with a byte of 0 if the record length is odd), and a trailing 32-bit record length.  File marks are recorded as one record length of 0.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Cards have 12 bits of data per column,\hich\af1\dbch\af31505\loch\f1 
 but the data is most conveniently viewed as (ASCII) characters.  Column binary can be implemented using two successive characters per card column..
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Data I/O varies between fixed and variable capacity devices, and between buffered and non-buffered devices\hich\af1\dbch\af31505\loch\f1 
.  A fixed capacity device differs from a variable capacity device in that the file attached to the former has a maximum size, while the file attached to the latter may expand indefinitely.  A buffered device differs from a non-buffered device in that the
\hich\af1\dbch\af31505\loch\f1  \hich\af1\dbch\af31505\loch\f1 
former buffers its data set in host memory, while the latter maintains it as a file.  Most variable capacity devices (such as the paper tape reader and punch) are sequential; all buffered devices are fixed capacity.
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.4.1\tab}}\pard \ltrpar\ql \fi-1080\li1080\ri0\widctlpar
\jclisttab\tx1080\wrapdefault\faauto\ls1\ilvl3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Reading and Writing Data
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The A\hich\af1\dbch\af31505\loch\f1 TTACH command creates an association between a host file and an I/O unit.  For non-buffered devices, ATTACH stores the file pointer for the host file in the }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fileref}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field of the UNIT structure.  For buffered devices, ATTACH reads the entire host file into 
\hich\af1\dbch\af31505\loch\f1 a buffer pointed to by the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 filebuf }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
field of the UNIT structure.  If unit flag UNIT_MUSTBUF is set, the buffer is allocated dynamically; otherwise, it must be statically allocated.
\par 
\par \hich\af1\dbch\af31505\loch\f1 For non-buffered devices, I/O is done with standard C subroutines plus the \hich\af1\dbch\af31505\loch\f1 SCP routines }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fread}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fwrite}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fread}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fwrite}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 are identical in calling sequence and function to fread and fwrite, respectively, but will correct for endian dependencies.  For buffered devices, I/O is done by copying data to or from the a\hich\af1\dbch\af31505\loch\f1 
llocated buffer.  The device code must maintain the number (+1) of the highest address modified in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 hwmark}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  field of the UNIT structure.  For both the non-buffered and buffered cases, the device must perform all address calculations and positioning opera\hich\af1\dbch\af31505\loch\f1 tions.
\par 
\par \hich\af1\dbch\af31505\loch\f1 
SIMH provides capabilities to access files >2GB (the int32 position limit).  If a VM is compiled with flags USE_INT64 and USE_ADDR64 defined, then t_addr is defined as t_uint64 rather than uint32.  Routine sim_fseek allows simulated devices to perf
\hich\af1\dbch\af31505\loch\f1 orm random access in large files:
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls24\adjustright\rin0\lin720\itap0 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fseek}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  (FILE *handle, t_addr position, int where)
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 sim_fseek is identical to standard C }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fseek}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
, with two exceptions: where = SEEK_END is not supported, and the position argument can be 64b wide.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The DETACH comman\hich\af1\dbch\af31505\loch\f1 d breaks the association between a host file and an I/O unit.  For buffered devices, DETACH writes the allocated buffer back to the host file.
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.4.2\tab}}\pard \ltrpar\ql \fi-1080\li1080\ri0\widctlpar
\jclisttab\tx1080\wrapdefault\faauto\ls1\ilvl3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Console I/O
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 SCP provides three routines for console I/O.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_poll_char }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (void).  This routine\hich\af1\dbch\af31505\loch\f1 
 polls for keyboard input.  If there is a character, it returns SCPE_KFLAG + the character.  If the user typed the interrupt character (^E), it returns SCPE_STOP.  If the console is attached to a Telnet connection, and the connection is lost, the routine 
\hich\af1\dbch\af31505\loch\f1 r\hich\af1\dbch\af31505\loch\f1 eturns SCPE_LOST.  If there is no input, it returns SCPE_OK.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_putchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (int32 char).  This routine types the specified ASCII character to the console.  If the console is attached to a Telnet connection, and the connection is lost, the routine \hich\af1\dbch\af31505\loch\f1 returns SCPE_LOST.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_putchar_s}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (int32 char).  This routine outputs the specified ASCII character to the console.  If the console is attached to a Telnet connection, and the connection is lost, the routine returns SCPE_LOST; if the connection i\hich\af1\dbch\af31505\loch\f1 
s backlogged, the routine returns SCPE_STALL.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\*\bkmkstart _Toc356355622}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Structures{\*\bkmkend _Toc356355622}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The devices, units, and registers that make up a VM are formally described through a set of data structures which interface the VM to the control portions of SCP. \hich\af1\dbch\af31505\loch\f1 
 The devices themselves are pointed to by the device list array }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  Within a device, both units and registers are allocated contiguously as arrays of structures.  In addition, many devices allow the user to set or clear options via a modificati\hich\af1\dbch\af31505\loch\f1 ons table.
\par 
\par \hich\af1\dbch\af31505\loch\f1 \hich\f1 Note that a device must always have at least one unit, even if that unit is not needed for simulation purposes.  A device must always point to a valid register table, but the register table can consist of just the 
\'93\loch\f1 \hich\f1 end of table\'94\loch\f1  entry.
\par {\*\bkmkstart _Toc356355623}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_device Structure{\*\bkmkend _Toc356355623}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Devices are defined by the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_device}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure (typedef 
}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEVICE}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_device \{
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *name;\tab \tab \tab \tab /* name */
\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_unit \tab *units;\tab \tab \tab \tab /* units */
\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_reg\tab *registers;\tab \tab \tab /* registers */
\par \tab \hich\af1\dbch\af31505\loch\f1 struct si\hich\af1\dbch\af31505\loch\f1 m_mtab\tab *modifiers;\tab \tab \tab /* modifiers */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab numunits;\tab \tab \tab /* #units */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab aradix;\tab \tab \tab \tab /* address radix */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab awidth;\tab \tab \tab \tab /* address width */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab aincr;\tab \tab \tab \tab /* addr increment */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dradix;\tab \tab \tab \tab /* data radix */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dwidth;\tab \tab \tab \tab /* data w\hich\af1\dbch\af31505\loch\f1 idth */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*examine)();\tab \tab \tab /* examine routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*deposit)();\tab \tab \tab /* deposit routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*reset)();\tab \tab \tab /* reset routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*boot)();\tab \tab \tab /* boot routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*attach)();\tab \tab \tab /* attach routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*detach)();\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* detach routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *ctxt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 ;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 * context */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dctrl;\tab \tab \tab \tab /* debug control flags */
\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_debtab debflags;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
* debug flag names */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*msize)();\tab \tab \tab /* memory size change */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *lname;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid399520 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1  logic\hich\af1\dbch\af31505\loch\f1 al name */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*help)();}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 
 help routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*attach_help)();}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 
 attach help routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *help_ctxt;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 
* help context */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 device name, string of all capital alphanumeric characters.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 units}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structures, or NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 registers}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structures, or NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 modifiers}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structures, or NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 numunits}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  \tab number of units in this device.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aradix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 radix for inp\hich\af1\dbch\af31505\loch\f1 
ut and display of device addresses, 2 to 16 inclusive.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of a device address, 1 to 64 inclusive.
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab 
\hich\af1\dbch\af31505\loch\f1 increment between device addresses, normally 1; however, byte addressed devices with 16-bit words specify 2, with 32-bit words 4.
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dradix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 radix for input and display of device data, 2 to 16 inclusive.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dwidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of device data, 1 to 64 inclusive.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 examine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of special device data read routine, or NULL if none is required.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 deposit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of special device data write \hich\af1\dbch\af31505\loch\f1 
routine, or NULL if none is required.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of device reset routine, or NULL if none is required.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 boot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of device bootstrap routine, or NULL if none is required.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of special device attach routine, or NULL if none is required.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of special device detach routine, or NULL if none is required.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ctxt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of VM-specific device context table, or NULL if none is required.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 device flags.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debug control flags.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pointer to array of sim_debtab struct\hich\af1\dbch\af31505\loch\f1 
ures, or NULL if none.
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid399520 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 msize}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 address of memory size change routine, or NULL if none is required.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 lname\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 pointer to logical name string.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of help routine, or NULL if none is required.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 attach_help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 address of attach help routine, or NULL if none
\hich\af1\dbch\af31505\loch\f1  is required.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 help_ctx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 address of device specific context }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid14750569 \hich\af1\dbch\af31505\loch\f1 which might be useful while displaying }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 help }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14750569 
\par }\pard \ltrpar\ql \li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid14750569 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14750569 \hich\af1\dbch\af31505\loch\f1 for the current device, or NULL if }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 none is required.
\par {\*\bkmkstart _Toc356355624}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Awidth and Aincr{\*\bkmkend _Toc356355624}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 
\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  field specifies the width of the VM\hich\f1 \rquote \loch\f1 s f\hich\af1\dbch\af31505\loch\f1 \hich\f1 undamental computer \'93\loch\f1 \hich\f1 word\'94\loch\f1 .  For example, on the PDP-11, }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is 16b, even though memory is byte-addressable.  The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1  field specifies how many addressing units comprise the fundamental \'93\loch\f1 \hich\f1 word\'94\loch\f1 
.  For example, on the PDP-11, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is 2 (\hich\af1\dbch\af31505\loch\f1 
2 bytes per word).
\par 
\par \hich\af1\dbch\af31505\loch\f1 If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is greater than 1, SCP assumes that data is naturally aligned on addresses that are multiples of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .  VM\hich\f1 \rquote \loch\f1 s that support arbitrary byte alignment of data (like the VAX) can follow one of two strategies:
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls24\adjustright\rin0\lin720\itap0 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  = 8 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 = 1 and support only byte access in the examine/deposit routines.
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth
}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  to the fundamental sizes and support unaligned data access in the examine/deposit routines.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 In a byte-addressable VM, SAVE and RESTORE will require (memory_size\hich\af1\dbch\af31505\loch\f1 _bytes / }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
) iterations to save or restore memory.  Thus, it is significantly more efficient to use word-wide rather than byte-wide memory; but requirements for unaligned access can add significantly to the complexity of the examine and deposit routines.
\par {\*\bkmkstart _Toc356355625}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Flags{\*\bkmkend _Toc356355625}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
field contains indicators of current device status.  SIMH defines }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 several }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag name\tab \tab meaning if set
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISABLE\tab \tab device can be set enabled or disabled
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DIS\tab \tab device is currently disable\hich\af1\dbch\af31505\loch\f1 d
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DYNM\tab \tab device requires call on }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 msize}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 routine to change memory size
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DEBUG\tab \tab device supports SET DEBUG command
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 
\par \hich\af1\dbch\af31505\loch\f1 The flags field also contains an optional device type specification.  One of these may be specified when initializing the flags field:
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISK\tab \tab device uses sim_disk library attach
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_TAPE\tab \tab device uses sim_tape library attach
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_MUX\tab \tab device uses sim_tmxr library attach
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_ETHER\tab \tab device uses sim_ether library attach
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISPLAY\tab \tab device uses sim_video library attach
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Starting at bit\hich\af1\dbch\af31505\loch\f1 
 position DEV_V_UF, the remaining flags are device-specific.  Device flags are automatically saved and restored; the device need not supply a register for these bits.
\par {\*\bkmkstart _Toc356355626}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Context{\*\bkmkend _Toc356355626}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The field contains a pointer to a VM-specific de\hich\af1\dbch\af31505\loch\f1 
vice context table, if required.  SIMH never accesses this field.  The context field allows VM-specific code to walk VM-specific data structures from the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices }{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 root pointer.
\par {\*\bkmkstart _Toc356355627}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Examine and Deposit Routines{\*\bkmkend _Toc356355627}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 
For devices which maintain their data sets as host files, SCP implements the examine and deposit data functions.  However, devices which maintain their data sets as private state (for example, the CPU) must supply special examine and deposit routines.  Th
\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1  calling sequences are:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 examine_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (t_val *eval_array, t_addr addr, UNIT *uptr, int32 switches) \hich\f1 \endash \loch\f1  Copy }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  consecutive addresses for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , starting at }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , into }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 eval_array}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The }{\rtlch\fcs1 
\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  variable has bit<n> set if the n\hich\f1 \rquote \loch\f1 th letter was 
\hich\af1\dbch\af31505\loch\f1 specified as a switch to the examine command.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 deposit_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (t_val value, t_addr addr, UNIT *uptr, int32 switches) \hich\f1 \endash \loch\f1  Store the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  in the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  for unit }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  variable is the same as for the examine routine.
\par {\*\bkmkstart _Toc356355628}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Reset Routine{\*\bkmkend _Toc356355628}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The reset routine implements the device reset function for the RESET, RUN, and BOOT commands.  Its calling sequence is:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reset_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (DEVICE *dptr) \hich\f1 
\endash \loch\f1  Reset the specified device to its initial state.
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 A ty\hich\af1\dbch\af31505\loch\f1 
pical reset routine clears all device flags and cancels any outstanding timing operations.  Switch \hich\f1 \endash \loch\f1 p specifies a reset to power-up state.
\par {\*\bkmkstart _Toc356355629}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.6\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Boot Routine{\*\bkmkend _Toc356355629}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If a device responds to a BOOT command, the boot routine implements the\hich\af1\dbch\af31505\loch\f1  bootstrapping function.  Its calling sequence is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 boot_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 unit_num, DEVICE *dptr) \hich\f1 \endash \loch\f1  Bootstrap unit  }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 unit_num}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  on the device }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 A typical bootstrap routine copies\hich\af1\dbch\af31505\loch\f1  a bootstrap loader into main memory and sets the PC to the starting address of the loader.  SCP then starts simulation at the specified address.
\par {\*\bkmkstart _Toc356355630}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.7\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Attach and Detach Routines{\*\bkmkend _Toc356355630}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Normally, the ATTACH and DETACH commands are handl\hich\af1\dbch\af31505\loch\f1 
ed by SCP.  However, devices which need to pre- or post-process these commands must supply special attach and detach routines.  The calling sequences are:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 attach_routine }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, char *file) \hich\f1 \endash \loch\f1  Attach the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 file}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to the unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 .
\par \hich\af1\dbch\af31505\loch\f1 Sim_swi\hich\af1\dbch\af31505\loch\f1 tches contains the command switch; bit SIM_SW_REST indicates that attach is being called by the RESTORE command rather than the ATTACH command.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Detach unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 In practice, these routines usually invoke the standard SCP routines, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 attach_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
, respectively.  For example, here are special attach and detach routines to update line printer error state:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 t_stat lpt_attach (UNIT *uptr, char *cptr) \{
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 t_s\hich\af2\dbch\af31505\loch\f2 tat r;
\par \hich\af2\dbch\af31505\loch\f2 if ((r = attach_unit (uptr, cptr)) != SCPE_OK) return r;
\par \hich\af2\dbch\af31505\loch\f2 lpt_error = 0;
\par \hich\af2\dbch\af31505\loch\f2 return SCPE_OK;
\par \}
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 
\par \hich\af2\dbch\af31505\loch\f2 t_stat lpt_detach (UNIT *uptr) \{
\par \tab \hich\af2\dbch\af31505\loch\f2 lpt_error = 1;
\par \tab \hich\af2\dbch\af31505\loch\f2 return detach_unit (uptr);
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \}
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If the VM specifies an ATTACH or DETACH routine, SCP bypasses its normal tests\hich\af1\dbch\af31505\loch\f1 
 before calling the VM routine.  Thus, a VM DETACH routine cannot be assured that the unit is actually attached and must test the unit flags if required.
\par 
\par \hich\af1\dbch\af31505\loch\f1 SCP executes a DETACH ALL command as part of simulator exit.  Normally, DETACH ALL only calls a unit\hich\f1 \rquote \hich\af1\dbch\af31505\loch\f1 s detach routine if the unit\hich\f1 \rquote \loch\f1 
s UNIT_ATT flag is set.  During simulator exit, the detach routine is also called if the unit is not flagged as attachable (UNIT_ATTABLE is not set).  This allows the detach routine of a non-attachable unit to function as a si
\hich\af1\dbch\af31505\loch\f1 m\hich\af1\dbch\af31505\loch\f1 ulator-specific cleanup routine for the unit, device, or entire simulator.
\par {\*\bkmkstart _Toc356355631}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.8\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Size Change Routine{\*\bkmkend _Toc356355631}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Most units instantiate any memory array at the maximum size possible.  This allows apparent memory size to be changed by \hich\af1\dbch\af31505\loch\f1 varying the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 field in the unit structure.  For some devices (like the VAX CPU), instantiating the maximum memory size would impose a significant resource burden if less memory was actually needed.  These devices must provide a routine, the memory size
\hich\af1\dbch\af31505\loch\f1  change routine, for RESTORE to use if memory size must be changed:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 change_mem_size}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  Change the capacity (memory size) of unit }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 arguments are included for compatibility\hich\af1\dbch\af31505\loch\f1  with the SET command\hich\f1 \rquote \loch\f1 s validation routine calling sequence.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\*\bkmkstart _Toc356355632}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.9\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Debug Controls{\*\bkmkend _Toc356355632}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Devices can support debug printouts.  Debug printouts are controlled by the SET \{NO\}DEBUG command,\hich\af1\dbch\af31505\loch\f1  which specifies where debug output should be printed; and by the SET <device> \{NO\}
DEBUG command, which enables or disables individual debug printouts.
\par 
\par \hich\af1\dbch\af31505\loch\f1 If a device supports debug printouts, device flag DEV_DEBUG must be set.  Field }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  is used for the d\hich\af1\dbch\af31505\loch\f1 ebug control flags.  If a device supports only a single debug on/off flag, then the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field should be set to NULL.  If a device supports multiple debug on/off flags, then the correspondence between bit positions in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and debug flag names is spec\hich\af1\dbch\af31505\loch\f1 ified by table  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to a continguous array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_debtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  structures (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEBTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
).  Each sim_debtab structure specifies a single debug flag:
\par 
\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid16013944 \hich\af1\dbch\af31505\loch\f1 s}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 truct sim_debtab \{
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab name}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab \tab /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
* flag name */
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab mask;\tab \tab \tab \tab /* control bit \hich\af1\dbch\af31505\loch\f1 */
\par \tab \tab \}\hich\af1\dbch\af31505\loch\f1 ;
\par 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 name\tab \tab name of the debug flag.
\par \tab \hich\af1\dbch\af31505\loch\f1 mask\tab \tab bit mask of the debug flag.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The array is terminated with a NULL entry.
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid8129972 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 Simulator code can produce debug output by calling }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid8084824 \hich\af1\dbch\af31505\loch\f1 sim_debug }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 which is declared:
\par 
\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid16013944 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 void}{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2  _}{\rtlch\fcs1 \af2 \ltrch\fcs0 \b\f2\lang1024\langfe1024\noproof\insrsid8129972\charrsid16013944 \hich\af2\dbch\af31505\loch\f2 sim_debug}{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2  (uint32 dbits, DEVICE* dptr, }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 const}{\rtlch\fcs1 \af2 
\ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2  }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 char}{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 * fmt, ...);
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid8129972 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8129972 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8129972\charrsid16013944 \hich\af1\dbch\af31505\loch\f1 The dbits is a flag which matches a mask in a sim_debtab structure, and the }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid8352301\charrsid16013944 \hich\af1\dbch\af31505\loch\f1 the dptr is the DEVICE which has the corresponding dctl field.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8129972\charrsid16013944 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8352301\charrsid16013944 
\par \hich\af1\dbch\af31505\loch\f1 Additionally support exists for displaying bit and bitfield va\hich\af1\dbch\af31505\loch\f1 lues.  Bit field values are defined using the BITFIELD}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid8084824\charrsid16013944 \hich\af1\dbch\af31505\loch\f1  structure and the BIT macros to declare the bits and bitfields.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8352301\charrsid16013944 

\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\rin0\lin720\itap0\pararsid16013944 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BIT(nm) }{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\lang1024\langfe1024\noproof\insrsid8084824 \tab \tab \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 - Single Bit definition}{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BITNC   }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \tab \tab \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 - Don't care Bit definition}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BITF(nm,sz) }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \tab \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 - Bit Field definition}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BITNCF(sz)}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \tab \tab \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 -}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2  Do}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 
\hich\af2\dbch\af31505\loch\f2 n't care Bit Field definition}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BITFFMT(nm,sz,fmt)}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2  \tab }{
\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 -}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2  Bit Field }{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 definition with Output format}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BITFNAM(nm,sz,names)}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 -}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2  Bit Field definition with va}{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 lue->name map}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 ENDBITS
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid16013944 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid16013944\charrsid16013944 \hich\af1\dbch\af31505\loch\f1 For example:
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\rin0\lin720\itap0\pararsid16013944 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 static}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2  }{\rtlch\fcs1 \af2 
\ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 const}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2  }{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\cf2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 char}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2  *rp_fname[CS1_N_FNC] = \{
\par \hich\af2\dbch\af31505\loch\f2     }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "NOP"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "UNLD"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "SEEK"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "RECAL"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "DCLR"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "RLS"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , 
\par \hich\af2\dbch\af31505\loch\f2     }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "OFFS"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "RETN"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 ,}{\rtlch\fcs1 \af2 
\ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "PRESET"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "PACK"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "SEARCH"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 , 
\par \hich\af2\dbch\af31505\loch\f2     }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "WRCHK"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "WRITE"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "WRHDR"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "READ"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "RDHDR"
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2     \};
\par 
\par \hich\af2\dbch\af31505\loch\f2 BITFIELD xx_csr_bits[] = \{
\par \hich\af2\dbch\af31505\loch\f2   BIT(GO),                                  }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 /* Go */
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2   BITFNAM(FUNC,5,rp_fname),                 }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 /* F\hich\af2\dbch\af31505\loch\f2 unction Code */
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2   BIT(IE),                                  }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 /* Interrupt Enable */
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2   BIT(RDY),                                 }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 /* Drive Ready */
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2   BIT(DVA),                                 }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 /* Drive Available */
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2   BITNCF(1),                                }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 /\hich\af2\dbch\af31505\loch\f2 * 12 Reserved */
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2   BIT(TRE),                                 }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 /* Transfer Error */
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2   BIT(SC),                                  }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 
\hich\af2\dbch\af31505\loch\f2 /* Special Condition */
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2   ENDBITS
\par \}\hich\af2\dbch\af31505\loch\f2 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid16013944 \hich\af1\dbch\af31505\loch\f1 The fields in a register can be displayed (along with transition indicators) by calling sim_\hich\af1\dbch\af31505\loch\f1 debug_bits.
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\rin0\lin720\itap0\pararsid16013944 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 void}{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2  }{\rtlch\fcs1 \af2 \ltrch\fcs0 \b\f2\lang1024\langfe1024\noproof\insrsid8084824\charrsid16013944 \hich\af2\dbch\af31505\loch\f2 sim_debug_bits}{\rtlch\fcs1 \af2 \ltrch\fcs0 
\f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2  (uint32 dbits, DEVICE* dptr, BITFIELD* bitdefs, uint32 before, uint32 after, }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid8084824 
\hich\af2\dbch\af31505\loch\f2 int}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2  terminate);
\par {\*\bkmkstart _Toc356355633}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 4.1.10\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid3867041 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \insrsid3867041 \hich\af1\dbch\af31505\loch\f1 Device Specific Help support{\*\bkmkend _Toc356355633}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid7174065 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid7174065 
\par \hich\af1\dbch\af31505\loch\f1 
A device declaration may specify a device type or class in the flags field by providing one of DEV_DISK, DEV_TAPE, DEV_MUX, DEV_ETHER or DEV_DISPLAY values when initializing the flags.  The device type allows the scp HELP command routine to provide some d
\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 fault help information for devices which don\hich\f1 \rquote \loch\f1 t otherwise specify a device specific help routine or a attach_help routine.
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7174065\charrsid7174065 
\par {\*\bkmkstart _Toc356355634}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 4.1.11\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid3867041 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \insrsid3867041 \hich\af1\dbch\af31505\loch\f1 Help Routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid14776269 {\*\bkmkend _Toc356355634}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid14776269 
\par \hich\af1\dbch\af31505\loch\f1 A device declaration may provide a routine which will display help about that device w\hich\af1\dbch\af31505\loch\f1 \hich\f1 hen a user enters a \'93\loch\f1 \hich\f1 HELP dev\'94\loch\f1  command.}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1   }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid3867041 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid3867041 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid3867041 
\hich\af1\dbch\af31505\loch\f1 help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1  (}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 FILE}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 
\hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 *st, DEVICE }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 d}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 ptr,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1  UNIT *uptr, }{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 , char *cptr) 
\hich\f1 \endash \loch\f1  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 Write help information about the device and/or unit usage.  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 The }
{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 flag and }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 
\hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 arguments are included for compatibility with the }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 HELP }{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 comma\hich\af1\dbch\af31505\loch\f1 nd\hich\f1 \rquote \loch\f1 s validation routine calling sequence.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 
\par {\*\bkmkstart _Toc356355635}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 4.1.12\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid14776269 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \insrsid14776269 \hich\af1\dbch\af31505\loch\f1 Attach Help Routine{\*\bkmkend _Toc356355635}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid14776269 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 A device declaration may provide a routine which will display help about h}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 
ORE to use if memory size must be changed:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid3867041 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 t_stat attach_}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid3867041 
\hich\af1\dbch\af31505\loch\f1 help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1  (FILE *st, DEVICE *dpt\hich\af1\dbch\af31505\loch\f1 r, UNIT *uptr, int32 flag, char *cptr) \hich\f1 \endash \loch\f1 
 Write help information about the device and/or unit attach usage.  The flag and }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 
 arguments are included for compatibility with the HELP command\hich\f1 \rquote \loch\f1 s validation routine calling sequence.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8084824 
\par {\*\bkmkstart _Toc356355636}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit \hich\af1\dbch\af31505\loch\f1 Structure{\*\bkmkend _Toc356355636}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Units are allocated as contiguous array.  Each unit is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_unit \{
\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_unit\tab *next;\tab \tab \tab \tab /* next active */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*action)();\tab \tab \tab /* action routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *filename;\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* open file name */
\par \tab \hich\af1\dbch\af31505\loch\f1 FILE\tab \tab *fileref;\tab \tab \tab \tab /* file reference */
\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *filebuf;\tab \tab \tab \tab /* memory buffer */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab hwmark;\tab \tab \tab /* high water mark */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab time;\tab \tab \tab \tab /* time out */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab capac;\tab \tab \tab \tab /* capacity */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab pos;\tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* file position */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab buf;\tab \tab \tab \tab /* buffer */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab wait;\tab \tab \tab \tab /* wait */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u3;\tab \tab \tab \tab /* device specific */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u4;\tab \tab \tab \tab /* device specific */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u5;\tab \tab \tab \tab /* device specific */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u6;\tab \tab \tab \tab /* device specific */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the follo\hich\af1\dbch\af31505\loch\f1 wing:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 next}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 pointer to next unit in active queue, NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 action}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of unit time-out service routine.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 filename}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to name of attached file, NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fileref}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to FILE structure of attached file, NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 hwmark}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 buffered d\hich\af1\dbch\af31505\loch\f1 
evices only; highest modified address, + 1.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 time}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 increment until time-out beyond previous unit in active queue.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 unit flags.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 unit capacity, 0 if variable.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pos}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 sequential devices only; next device address to be read or written.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 by convention, the unit buffer, but can be used for other purposes.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 wait}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 by convention, the unit wait time, but can be used for other purposes.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u3}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 user-defined.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u4}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 user-defined.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u5\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 user-defined.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u6\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 user-defined.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 buf, wait, u3, u4, u5, u6, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and parts o\hich\af1\dbch\af31505\loch\f1 f }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  are all saved and restored by the SAVE and RESTORE commands and thus can be used for unit state which must be preserved.
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 UDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is available to fill in the common fields of a UNIT.  It is invoked by
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \tab \hich\af1\dbch\af31505\loch\f1 UDATA\tab \tab (action_routine, flags, capacity)
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Fields after }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  can be filled in manually, e.g,
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 UNIT lpt_unit = 
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2  UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE, 0), 500 \};
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 defines the line printer as a sequential unit with a wait time of 500.
\par {\*\bkmkstart _Toc356355637}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Unit Flags{\*\bkmkend _Toc356355637}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field co\hich\af1\dbch\af31505\loch\f1 
ntains indicators of current unit status.  SIMH defines 12 flags:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag name\tab \tab meaning if set
\par 
\par \hich\af1\dbch\af31505\loch\f1 UNIT_ATTABLE\tab the unit responds to ATTACH and DETACH.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_RO\tab \tab the unit is currently read only.
\par \hich\af1\dbch\af31505\loch\f1 UNIX_FIX\tab \tab the unit is fixed capacity.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_SEQ\tab \tab \hich\af1\dbch\af31505\loch\f1 the unit is sequential.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_ATT\tab \tab the unit is currently attached to a file.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_BINK\tab \tab \hich\f1 the unit measures \'93\loch\f1 \hich\f1 K\'94\loch\f1  as 1024, rather than 1000.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_BUFABLE\tab the unit buffers its data set in memory.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_MUSTBUF\tab the unit allocates its data buffer dynamically.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_\hich\af1\dbch\af31505\loch\f1 BUF\tab \tab the unit is currently buffering its data set in memory.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_ROABLE\tab \tab the unit can be ATTACHed read only.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_DISABLE\tab \tab the unit responds to ENABLE and DISABLE.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_DIS\tab \tab the unit is currently disabled.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_RAW\tab \tab the unit is attached in RAW mode.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Star\hich\af1\dbch\af31505\loch\f1 
ting at bit position UNIT_V_UF, the remaining flags are unit-specific.  Unit-specific flags are set and cleared with the SET and CLEAR commands, which reference the MTAB array (see below).  Unit-specific flags and UNIT_DIS are automatically saved and rest
\hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 red; the device need not supply a register for these bits.
\par {\*\bkmkstart _Toc356355638}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Service Routine{\*\bkmkend _Toc356355638}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 This routine is called by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 when a unit times out.  Its calling sequence is:
\par 
\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 service_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr)
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The status return\hich\af1\dbch\af31505\loch\f1 
ed by the service routine is passed by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  back to the CPU.
\par {\*\bkmkstart _Toc356355639}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg Structure{\*\bkmkend _Toc356355639}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Registers are allocated as contiguous array, with a NULL register at the end.  Each register is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure (typ\hich\af1\dbch\af31505\loch\f1 edef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct reg \{
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *name;\tab \tab \tab \tab /* name */
\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *loc;\tab \tab \tab \tab /* location */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab radix;\tab \tab \tab \tab /* radix */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab width;\tab \tab \tab \tab /* width */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab offset;\tab \tab \tab \tab /* starting bit */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab depth;\tab \tab \tab \tab /* save depth */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */
\par \tab \hich\af1\dbch\af31505\loch\f1 uin\hich\af1\dbch\af31505\loch\f1 t32\tab \tab qptr;\tab \tab \tab \tab /* current queue pointer */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 device name, string of all capital alphanumeric characters.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 loc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to location of the register value.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 radix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 radix for input and display of data, 2 to 16 inclusive.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 wi\hich\af1\dbch\af31505\loch\f1 dth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of data, 1 to 32 inclusive.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 width\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 bit offset (from right end of data).
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 depth\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 size of data array (normally 1).
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 flags and formatting information.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 qptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 for a circular queue, the entry number for the first entry
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 depth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field\hich\af1\dbch\af31505\loch\f1 \hich\f1 
 is used with \'93\loch\f1 \hich\f1 arrayed registers\'94\loch\f1 
.  Arrayed registers are used to represent structures with multiple data values, such as the locations in a transfer buffer; or structures which are replicated in every unit, such as a drive status register.  The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 qptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field\hich\af1\dbch\af31505\loch\f1 \hich\f1  is used with \'93\loch\f1 \hich\f1 queued registers\'94\loch\f1 
.  Queued registers are arrays that are organized as circular queues, such as the PC change queue.
\par 
\par \hich\af1\dbch\af31505\loch\f1 A register that is 32b or less keeps its data in a 32b scalar variable (signed or unsigned).  A register that is 33b or more\hich\af1\dbch\af31505\loch\f1 
 keeps its data in a 64b scalar variable (signed or unsigned).  There are several exceptions to this rule:
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls27\adjustright\rin0\lin720\itap0 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
An arrayed register keeps its data in a C-array whose SIMH data type is as large as (or if necessary, larger than), the width of a register element.  For example, an array of 6b registers would keep its data in a uint8 (or int8) array; an array of 16b reg
\hich\af1\dbch\af31505\loch\f1 i\hich\af1\dbch\af31505\loch\f1 sters would keep its data in a uint16 (or int16) array; an array of 24b registers would keep its data in a uint32 (or int32) array.
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 
A register flagged with REG_FIT obeys the sizing rules of an arrayed register, rather than a normal scalar register.  This\hich\af1\dbch\af31505\loch\f1  is useful for aliasing registers into memory or into structures.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Macros }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ORDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DRDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 HRDATA}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  define right-justified octal, decimal, and hexidecimal registers, respectively.  They are invoked by:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 xRDATA\tab (name, location, width)
\par 
\par \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 FLDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  define\hich\af1\dbch\af31505\loch\f1 
s a one-bit binary flag at an arbitrary offset in a 32-bit word.  It is invoked by:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 FLDATA\tab (name, location, bit_position)
\par 
\par \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 GRDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 defines a register with arbitrary location and radix.  It is invoked by:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 GRDATA\tab (name, location, radix, width, bit_p\hich\af1\dbch\af31505\loch\f1 osition)
\par 
\par \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 BRDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 defines an arrayed register whose data is kept in a standard C array.  It is invoked by:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 BRDATA\tab (name, location, radix, width, depth)
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 For all of these macros, the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field can be filled in manually, e.g.,
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 REG lpt_reg = \{
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \tab \{\hich\af2\dbch\af31505\loch\f2  D\hich\af2\dbch\af31505\loch\f2 RDATA\tab (POS, lpt_unit.pos, 31), PV_LFT \}
\hich\f2 , \'85\loch\f2  \}
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Finally, macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 URDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 defines an arrayed register whose data is part of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 structure.  This macro must be used with great care.  If the fields are set up wrong, or the data is actually kept somewhere else\hich\af1\dbch\af31505\loch\f1 , storing through this register declaration can trample over memory.  The macro is invoked by:

\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 URDATA\tab (name, location, radix, width, offset, depth, flags)
\par 
\par \hich\af1\dbch\af31505\loch\f1 The location should be an offset in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
structure for unit 0.  The width should be 32 for an int32 or uint32 field, and T_ADDR_W for a t_addr filed.  The flags can be any of the normal register flags; REG_UNIT will be OR\hich\f1 \rquote \loch\f1 
d in automatically.  For example, the following declares an arrayed regist\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 r of all the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT }{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 position fields in a device with 4 units:
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \{\hich\af2\dbch\af31505\loch\f2  URDATA\tab (POS, dev_unit[0].pos, 8, T_ADDR_W, 0, 4, 0) \}
\par {\*\bkmkstart _Toc356355640}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.3.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Register Flags{\*\bkmkend _Toc356355640}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field contains indicators that control register examination and deposit.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag n\hich\af1\dbch\af31505\loch\f1 ame\tab \tab meaning if specified
\par 
\par \hich\af1\dbch\af31505\loch\f1 PV_RZRO\tab \tab print register right justified with leading zeroes.
\par \hich\af1\dbch\af31505\loch\f1 PV_RSPC\tab \tab print register right justified with leading spaces.
\par \hich\af1\dbch\af31505\loch\f1 PV_LEFT\tab \tab print register left justified.
\par \hich\af1\dbch\af31505\loch\f1 REG_RO\tab \tab register is read only.
\par \hich\af1\dbch\af31505\loch\f1 REG_HIDDEN\tab \tab register is hidden (will\hich\af1\dbch\af31505\loch\f1  not appear in EXAMINE STATE).
\par \hich\af1\dbch\af31505\loch\f1 REG_HRO\tab \tab register is read only and hidden.
\par \hich\af1\dbch\af31505\loch\f1 REG_NZ\tab \tab new register values must be non-zero.
\par \hich\af1\dbch\af31505\loch\f1 REG_UNIT\tab \tab register resides in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure.

\par \hich\af1\dbch\af31505\loch\f1 REG_CIRC\tab \tab register is a circular queue.
\par \hich\af1\dbch\af31505\loch\f1 REG_VMIO\tab \tab register is displayed and parsed usi\hich\af1\dbch\af31505\loch\f1 ng VM data routines.
\par \hich\af1\dbch\af31505\loch\f1 REG_VMAD\tab \tab register is displayed and parsed using VM address routines.
\par \hich\af1\dbch\af31505\loch\f1 REG_FIT\tab \tab register container uses arrayed rather than scalar size rules.
\par {\*\bkmkstart _Toc356355641}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab Structure{\*\bkmkend _Toc356355641}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device-specific SHOW and SET commands are p\hich\af1\dbch\af31505\loch\f1 
rocessed using the modifications array, which is allocated as contiguous array, with a NULL at the end.  Each possible modification is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure (synonym }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ), which has the following fields:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_mtab \{
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab mask;\tab \tab \tab \tab /*\hich\af1\dbch\af31505\loch\f1  mask */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab match;\tab \tab \tab \tab /* match */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *pstring;\tab \tab \tab /* print string */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *mstring;\tab \tab \tab /* match string */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*valid)();\tab \tab \tab /* validation routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*disp)();\tab \tab \tab /* display routine */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11095770 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *desc}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid11095770 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab \tab /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \hich\af1\dbch\af31505\loch\f1 * location descriptor */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \hich\af1\dbch\af31505\loch\f1 char}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \hich\af1\dbch\af31505\loch\f1 help}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ;\tab 
\tab \tab \tab /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 * }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \hich\af1\dbch\af31505\loch\f1 help string }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 MTAB supports two different structure interpretations: regular and extended.  A regular MTAB entry modifies flags in the UNIT flags word; the descriptor entry is not used.  The fields are the following:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 bit mask for\hich\af1\dbch\af31505\loch\f1  testing the unit.}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  field
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab 
\hich\af1\dbch\af31505\loch\f1 value to be stored (SET) or compared (SHOW)
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string printed on a match (SHOW), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string to be matched (SET), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 valid}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of validation routine (SET\hich\af1\dbch\af31505\loch\f1 ), or NULL

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 disp\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 address of display routine (SHOW), or NULL
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 For SET, a regular MTAB entry is interpreted as follows:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  entry exists.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the SET parameter matches the }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Call the validation routine, if any.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Apply the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  value to the UNIT flags word and then or in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  value. 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 For SHOW, a regular MTAB entry is interpreted as follows:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  entry exists.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the UNIT flags word, masked with the }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  value, equals the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  value.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If a display routine exists, call it, otherwise
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Print the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Extended MTAB entries have a different interpretation:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 entry flags
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB_XTD\tab extende\hich\af1\dbch\af31505\loch\f1 d entry
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VDV\tab valid for devices
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VUN\tab valid for units
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11095770 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VALR\tab requires a value
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VAL}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 
\hich\af1\dbch\af31505\loch\f1 O}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \hich\af1\dbch\af31505\loch\f1 optionally requires }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 a value
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_NMO\tab valid only in named SHOW
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_NC\tab do not convert option value to upper case
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_SHP\tab SHOW parameter takes opt\hich\af1\dbch\af31505\loch\f1 ional value
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab 
\hich\af1\dbch\af31505\loch\f1 value to be stored (SET)
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string printed on a match (SHOW), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string to be matched (SET), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 valid}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of validation routine (SET), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 disp\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 address of display ro\hich\af1\dbch\af31505\loch\f1 utine (SHOW), or NULL

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pointer to a REG structure (MTAB_VAL set) or
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 a validation-specific structure (MTAB_VAL clear)
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 For SET, an extended MTAB entry is interpreted as follows:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  entry exists.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the SET parameter matches the }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Test to see if the entry is valid for the type of SET being done (SET device or SET unit).
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
If a validation routine exists, call it and return its status.  The validation routine is responsible f\hich\af1\dbch\af31505\loch\f1 or storing the result. 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is NULL, exit.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 If MTAB_VAL is set, parse the SET option for \'93\loch\f1 \hich\f1 
option=n\'94\loch\f1 , and store the value n in the register described by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 7.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Otherwise, store the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  value in the int32 pointed to by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 For SHOW, an extended MTAB entry is interpreted as follows:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  entry exists.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Test to see if the entry is valid for the type of SHOW being done (device or unit).
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If a display routine exists, call it, otherwise,
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If MT\hich\af1\dbch\af31505\loch\f1 \hich\f1 AB_VAL is set, print \'93
\loch\f1 \hich\f1 pstring=n\'94\loch\f1 , where the value, radix, and width are taken from the register described by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , otherwise,
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Print the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SHOW [dev|unit] <modifier>\{=<value>\} is a special case.  Only two kinds of modifiers can be displayed indi\hich\af1\dbch\af31505\loch\f1 
vidually: an extended MTAB entry that takes a value; and any MTAB entry with both a display routine and a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .  Recall that if a display routine exists, SHOW does not use the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  entry.  For displaying a named modifier, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is used as the strin\hich\af1\dbch\af31505\loch\f1 g match.  This allows implementation of complex display routines that are only invoked by name, e.g.,
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 MTAB cpu_tab[] = \{
\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  mask, value, \'93\loch\f2 \hich\f2 normal\'94\loch\f2 \hich\f2 , \'93\loch\f2 \hich\f2 NORMAL\'94\loch\f2 , NULL, NULL, NULL \},
\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, \'93\loch\f2 \hich\f2 SPECIAL\'94,
\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 NULL, NULL, NULL, &spec_disp \},
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \tab \{\hich\af2\dbch\af31505\loch\f2  0 \}
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \}\hich\af2\dbch\af31505\loch\f2 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 A SHOW CPU command will display only the modifier named NORMAL; but SHOW CPU SPECIAL will invoke the special display routine.
\par {\*\bkmkstart _Toc356355642}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Validation Routine{\*\bkmkend _Toc356355642}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The validation routine can be used to validate input during SET processing.  It can make other state changes required by the modification or initiate additional dialogs needed by the modifier.  Its calling sequence is:

\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 validation_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *upt\hich\af1\dbch\af31505\loch\f1 r, int32 value, char *cptr, void *desc) \hich\f1 \endash \loch\f1  test that }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  can be set to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 points to the value portion of the parameter string (any characters after the = sign); if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  is NULL, no value was given.  }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to the }{
\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  or int32 used to s\hich\af1\dbch\af31505\loch\f1 tore the parameter.
\par {\*\bkmkstart _Toc356355643}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Display Routine{\*\bkmkend _Toc356355643}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The display routine is called during SHOW processing to display device- or unit-specific state.  Its calling sequence is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 display_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *st, UNIT *uptr, int value, void *d\hich\af1\dbch\af31505\loch\f1 esc) \hich\f1 \endash \loch\f1 
 output device- or unit-specific state for }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to stream }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  If the modifier is regular MTAB entry, or an extended entry without MTAB_SHP set, }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to the structure in the MTAB entry.  If the modifier is an extended MTAB entry with MTAB_SHP 
\hich\af1\dbch\af31505\loch\f1 set, }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 points to the optional value string or is NULL if no value was supplied.  }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is the value field of the matched MTAB entry.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 When the display routine is called for a regular MTAB entry, SHOW has output the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  argument but has not appended a newline.  When it is called for an extended MTAB entry, SHOW hasn\hich\f1 \rquote \loch\f1 
t output anything.  SHOW will append a newline after the display routine returns, except for entries with the MTAB_NMO flag set.
\par {\*\bkmkstart _Toc356355644}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid14383756 \hich\af1\dbch\af31505\loch\f1 4.4.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid14383756 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \insrsid14383756 \hich\af1\dbch\af31505\loch\f1 Help Flag\hich\af1\dbch\af31505\loch\f1 s{\*\bkmkend _Toc356355644}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9796111 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af0 \ltrch\fcs0 \insrsid14383756 
\par \hich\af0\dbch\af31505\loch\f0 
The flags MTAB_VALR and MTAB_VALO are used to construct command syntax examples when displaying help for SET and SHOW commands.  These flags do not otherwise influence the actions taken during processing of SET or SHOW commands.
\par {\*\bkmkstart _Toc356355645}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid14383756 \hich\af1\dbch\af31505\loch\f1 4.4.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid14383756 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \insrsid14383756 \hich\af1\dbch\af31505\loch\f1 Example arguments in the }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid14383756\charrsid9796111 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid14383756 
{\*\bkmkend _Toc356355645}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9796111 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af0 \ltrch\fcs0 \insrsid14383756 
\par \hich\af0\dbch\af31505\loch\f0 The value of the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\insrsid14383756\charrsid9796111 \hich\af0\dbch\af31505\loch\f0 mstring}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14383756 \hich\af0\dbch\af31505\loch\f0 
 field may contain examples of valid additional parameters which may be specified as values.  For example:
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14383756 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid14383756 \tab \hich\af2\dbch\af31505\loch\f2 MTAB cr_mod[] = \{
\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  mask, value, \'93\loch\f2 \hich\f2 normal\'94\loch\f2 \hich\f2 , \'93\loch\f2 \hich\f2 NORMAL\'94\hich\af2\dbch\af31505\loch\f2 , NULL, NULL, NULL \},
\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  MTAB_XTD|MTAB_VDV, 0, \'93\loch\f2 \hich\f2 TRANSLATION\'94,
\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0\pararsid14383756 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid873649 \loch\af2\dbch\af31505\hich\f2 \'93\loch\f2 TRANSLATION=\{DEFAULT|026|026FTN|029|EBCDIC\}
\hich\f2 \'94}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid14383756 ,
\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0\pararsid873649 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid873649 \hich\af2\dbch\af31505\loch\f2 NULL, &cr_set_trans, &cr_show_trans \},
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14383756 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid14383756 \tab \tab \{\hich\af2\dbch\af31505\loch\f2  0 \}
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid14383756 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid14383756 \}\hich\af2\dbch\af31505\loch\f2 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9796111 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14383756 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 \hich\af0\dbch\af31505\loch\f0 This entry has an }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\insrsid873649\charrsid9796111 \hich\af0\dbch\af31505\loch\f0 mstring}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 
\hich\af0\dbch\af31505\loch\f0 \hich\f0  value of  \'93}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid873649 \hich\af2\dbch\af31505\loch\f2 TRANSLATION=\{DEFAULT|026|026FTN|029|EBCDIC\}}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 
\loch\af0\dbch\af31505\hich\f0 \'94\loch\f0 .  When compar\hich\af0\dbch\af31505\loch\f0 
isons are made against this string, everything starting at the equal sign and beyond is irrelevant to the match activity since the input being compared has already been parsed with a delimiter of \hich\f0 \lquote \loch\f0 =\hich\f0 \rquote \loch\f0 
.  The remaining parts of the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\insrsid873649\charrsid9796111 \hich\af0\dbch\af31505\loch\f0 mstring}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 \hich\af0\dbch\af31505\loch\f0  value are ignored, 
\hich\af0\dbch\af31505\loch\f0 but are available when constructing HELP dev SET output.}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649\charrsid9796111 
\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14383756\charrsid9796111 
\par {\*\bkmkstart _Toc356355646}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid873649 \hich\af1\dbch\af31505\loch\f1 4.4.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid873649 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid873649 \hich\af1\dbch\af31505\loch\f1 Help field{\*\bkmkend _Toc356355646}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9796111 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af0 \ltrch\fcs0 \insrsid873649 
\par \hich\af0\dbch\af31505\loch\f0 The MTAB entry\hich\f0 \rquote \loch\f0 s help field is used when constructing HELP dev SHOW or HELP dev SHOW output.  It serves to describe the purpose or effect of the particula\hich\af0\dbch\af31505\loch\f0 
r SET dev or SHOW dev command.  The help field is ignored when constructing HELP dev SET output for MTAB entries which have an equal sign in the mstring field. }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649\charrsid9796111 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14383756 
\par {\*\bkmkstart _Toc356355647}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.5\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other Data Structures{\*\bkmkend _Toc356355647}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_name[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is a character array cont
\hich\af1\dbch\af31505\loch\f1 aining the VM name.
\par 
\par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 contains the maximum number of words needed to hold the largest instruction or data item in the VM.  Examine and deposit will process up to }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  words.
\par 
\par \hich\af1\dbch\af31505\loch\f1 DEVICE *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is an array of pointers to all the device\hich\af1\dbch\af31505\loch\f1 s in the VM.  It is terminated by a NULL.  By convention, the CPU is always the first device in the array.
\par 
\par \hich\af1\dbch\af31505\loch\f1 REG *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_PC}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to the }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure for the program counter.  By convention, the PC is always the first register in the CPU\hich\f1 
\rquote \loch\f1 s register array.
\par 
\par \hich\af1\dbch\af31505\loch\f1 char *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_messages[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is an array of pointers to character strings, corresponding to error status returns greater than zero.  If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  returns status code n > 0, then }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_message[n]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is printed by SCP.
\par 
\par {\*\bkmkstart _Toc356355648}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Provided Routines{\*\bkmkend _Toc356355648}
\par {\*\bkmkstart _Toc356355649}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution{\*\bkmkend _Toc356355649}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Instruction execution is performed by routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  Its calling sequence is:
\par 
\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (void) \hich\f1 \endash \loch\f1  execute from current PC until error or halt.
\par {\*\bkmkstart _Toc356355650}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Binary Load and D\hich\af1\dbch\af31505\loch\f1 ump{\*\bkmkend _Toc356355650}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If the VM responds to the LOAD (or DUMP) command, the load routine (dump routine) is implemented by routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Its calling sequence is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *fptr, char *buf, char *fnam, t_bool flag) - If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  = 0, load data fro\hich\af1\dbch\af31505\loch\f1 m binary file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 fptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  = 1, dump data to binary file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  For either command, }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  contains any VM-specific arguments, and }{\rtlch\fcs1 
\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fnam}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  contains the file name.  
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If LOAD or DUMP is not implemented, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 should simply return SCPE_ARG.  The LOAD and DUMP\hich\af1\dbch\af31505\loch\f1  commands open and close the specified file for }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 .
\par {\*\bkmkstart _Toc356355651}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Symbolic Examination and Deposit{\*\bkmkend _Toc356355651}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If the VM provides symbolic examination and deposit of data, it must provide two routines, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  for output and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  for inp
\hich\af1\dbch\af31505\loch\f1 ut.  Their calling sequences are:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 switch) \hich\f1 \endash \loch\f1  Based on the }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  variable, symbolically output to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ofile}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  the data in array }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  at the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 in unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pa\hich\af1\dbch\af31505\loch\f1 rse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 switch) \hich\f1 \endash \loch\f1  Based on the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  variable, parse character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 for a symbolic value }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  at the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  in unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If symbolic processing is not implemented, or the output val\hich\af1\dbch\af31505\loch\f1 
ue or input string cannot be parsed, these routines should return SCPE_ARG.  If the processing was successful and consumed more than a single word, then these routines should return extra number of addressing units consumed as a }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 negative}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  number.  If the pr\hich\af1\dbch\af31505\loch\f1 
ocessing was successful and consumed a single addressing unit, then these routines should return SCPE_OK.  For example, PDP-11 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  would respond as follows to various inputs:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 input\tab \tab \tab \tab return value
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 XYZGH\tab \tab \tab \tab SCPE_ARG
\par \tab \hich\af1\dbch\af31505\loch\f1 MOV R0,R1\tab \tab \tab -1
\par \tab \hich\af1\dbch\af31505\loch\f1 MOV #4,R5\tab \tab \tab -3
\par \tab \hich\af1\dbch\af31505\loch\f1 MOV 1234,5670\tab \tab -5
\par 
\par \hich\af1\dbch\af31505\loch\f1 There is an implicit relationship between the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{
\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  arguments and the device\hich\f1 \rquote \loch\f1 s }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  fields.  Each entry in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is assumed to represent }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  addressing units, starting at }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :
\par 
\par \ltrrow}\trowd \irow0\irowband0\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
\trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[0]\cell \hich\af1\dbch\af31505\loch\f1 addr + 0\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow0\irowband0\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
\trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 
{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[1]\cell \hich\af1\dbch\af31505\loch\f1 addr + aincr\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1
\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow1\irowband1\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 
\trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr
\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow
}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[2]\cell \hich\af1\dbch\af31505\loch\f1 addr\hich\af1\dbch\af31505\loch\f1 
 + (2 * aincr)\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow2\irowband2\ltrrow\ts11\trgaph108\trleft1350\trbrdrt
\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 
\clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 
\cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[3]\cell 
\hich\af1\dbch\af31505\loch\f1 addr + (3 * aincr)\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow3\irowband3\ltrrow
\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr
\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :\cell 
\hich\af1\dbch\af31505\loch\f1 :\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow4\irowband4\lastrow \ltrrow
\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr
\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Because }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is typically filled in and stored by calls on the device\hich\f1 \rquote \loch\f1 s examine and deposit routines, respectively, the examine and deposit routines and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  fparse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  must agree on the expected width of items in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
, and on the alignment of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Further, if }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fparse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  wants to modify a storage unit narrower than }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , it must insert the new data into the appropriate entry in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  without destroying surrounding field\hich\af1\dbch\af31505\loch\f1 s.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The interpretation of switch values is arbitrary, but the following are used by existing VM\hich\f1 \rquote \loch\f1 s:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 switch\tab \tab \tab \tab interpretation
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 -a\tab \tab \tab \tab single character
\par \tab \hich\af1\dbch\af31505\loch\f1 -c\tab \tab \tab \tab character string
\par \tab \hich\af1\dbch\af31505\loch\f1 -m\tab \tab \tab \tab instruction mnemonic
\par 
\par \hich\af1\dbch\af31505\loch\f1 In addition, on input, a leading \hich\f1 \lquote \loch\f1  (apostrophe) is i\hich\af1\dbch\af31505\loch\f1 \hich\f1 nterpreted to mean a single character, and a leading \'93\loch\f1 
 (double quote) is interpreted to mean a character string.
\par {\*\bkmkstart _Toc356355652}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Optional Interfaces{\*\bkmkend _Toc356355652}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 For greater flexibility, SCP provides some optional interfaces that can be used to extend it\hich\af1\dbch\af31505\loch\f1 
s command input, command processing, and command post-processing capabilities.  These interfaces are strictly optional and are off by default.  Using them requires intimate knowledge of how SCP functions internally and is not recommended to the novice VM 
\hich\af1\dbch\af31505\loch\f1 w\hich\af1\dbch\af31505\loch\f1 riter.
\par {\*\bkmkstart _Toc356355653}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Once Only Initialization Routine{\*\bkmkend _Toc356355653}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 
)(void).  This is a \'93\loch\f1 \hich\f1 weak global\'94\loch\f1 ; if no other module defines this value, it will default to NULL.  A VM requiring special initialization should fil\hich\af1\dbch\af31505\loch\f1 
l in this pointer with the address of its special initialization routine:
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 void sim_special_init (void);
\par \tab \hich\af2\dbch\af31505\loch\f2 void (*sim_vm_init)(void) = &sim_special_init;
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 
The special initialization routine can perform any actions required by the VM.  If the other optional interfaces are to be used, the initialization routine can fill in the appropriate pointers; however, this can just as easily be done in the CPU reset rou
\hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 ine.
\par {\*\bkmkstart _Toc356355654}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Address Input and Display{\*\bkmkend _Toc356355654}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer t_addr *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
)(DEVICE *, char *, char **).  This is initialized to NULL.  If it is filled in by the VM, SCP will use the specified routine to parse addresses\hich\af1\dbch\af31505\loch\f1 
 in place of its standard numerical input routine.  The calling sequence for the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  routine is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_addr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (DEVICE *dptr, char *cptr, char **optr) \hich\f1 \endash \loch\f1  parse the string pointed to by }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  as an address for the device pointed to b\hich\af1\dbch\af31505\loch\f1 y }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  o}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ptr}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to the first character not successfully parsed.  If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  == }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 optr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , parsing failed.

\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer void *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
)(FILE *, DEVICE *, t_addr).  This is initialized to NULL.  If it is filled in by the VM, SCP will use th\hich\af1\dbch\af31505\loch\f1 
e specified routine to print addresses in place of its standard numerical output routine.  The calling sequence for the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  routine is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_addr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *stream, DEVICE *dptr, t_addr addr) \hich\f1 \endash \loch\f1  output address }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 stream}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  in t\hich\af1\dbch\af31505\loch\f1 he format required by the device pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 .
\par {\*\bkmkstart _Toc356355655}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Command Input and Post-Processing{\*\bkmkend _Toc356355655}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer char* (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
)(char *, int32 *, FILE *).  This is initialized to NULL.  If it is filled in by the VM, SCP wil\hich\af1\dbch\af31505\loch\f1 l use the specified routine to obtain command input in place of its standard routine, read_line.  The calling sequence for the }
{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  routine is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_vm_input}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (char *buf, int32 *max, FILE *stream) \hich\f1 \endash \loch\f1  read the next command line from }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 stream}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and sto\hich\af1\dbch\af31505\loch\f1 re it in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , up to a maximum of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  characters
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The routine is expected to strip off leading whitespace characters and to return NULL on end of file.
\par 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer void *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_post}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
)(t_bool from_scp).  This is initialized to NULL.  If filled in \hich\af1\dbch\af31505\loch\f1 
by the VM, SCP will call the specified routine at the end of every command.  This allows the VM to update any local state, such as a GUI console display.  The calling sequence for the vm_post routine is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_vm_postupdate}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (t_bool from_scp) \hich\f1 \endash \loch\f1  if calle\hich\af1\dbch\af31505\loch\f1 d from SCP, the argument }{\rtlch\fcs1 
\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 from_scp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is TRUE; otherwise, it is FALSE.
\par {\*\bkmkstart _Toc356355656}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM-Specific Commands{\*\bkmkend _Toc356355656}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer CTAB *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_cmd}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  T
\hich\af1\dbch\af31505\loch\f1 his is initialized to NULL.  If filled in by the VM, SCP interprets it as a pointer to SCP command table.  This command table is checked before user input is looked up in the standard command table.
\par 
\par \hich\af1\dbch\af31505\loch\f1 A command table is allocated as a contiguous \hich\af1\dbch\af31505\loch\f1 array.  Each entry is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_ctab}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_ctab \{
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *name;\tab \tab \tab \tab /* name */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*action)();\tab \tab \tab /* action routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab arg;\tab \tab \tab \tab /* argument */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *help;\tab \tab \tab \tab /* help string */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If the first word of a\hich\af1\dbch\af31505\loch\f1  command line matches ctab.name, then the action routine is called with the following arguments:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 action_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 arg, char *buf) \hich\f1 \endash \loch\f1  process input string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  based on optional argument }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 arg}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The string passed to the action routine starts at the \hich\af1\dbch\af31505\loch\f1 first non-blank character past the command name.
\par {\*\bkmkstart _Toc356355657}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other SCP Facilities{\*\bkmkend _Toc356355657}
\par {\*\bkmkstart _Toc356355658}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Input/Output Formatting Library{\*\bkmkend _Toc356355658}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SIMH provides routines to convert ASCII input characters to the format expected VM, a\hich\af1\dbch\af31505\loch\f1 nd to convert VM-supplied ASCII characters to C-standard format.  The routines are
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_tt_inpcvt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 c, uint32 mode) \hich\f1 \endash \loch\f1  convert input character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 c}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  according to the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mode }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 specification and return the converted result (-1 if the character is not valid\hich\af1\dbch\af31505\loch\f1  in the specified mode).
\par 
\par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_outcvt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 c, uint32 mode) \hich\f1 
\endash \loch\f1  convert output character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 c}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  according to the }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  specification and return the converted result (-1 if the character is not valid in the specified mode).

\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The supported modes are:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF\hich\af1\dbch\af31505\loch\f1 _MODE_8B\tab 8b mode; no conversion
\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_7B\tab 7b mode; the high-order bit is masked off
\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_7P\tab 7b printable mode; the high-order bit is masked off
\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 In addition, on output, if the character is not printable,
\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 -1 is returned
\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_UC\tab 7\hich\af1\dbch\af31505\loch\f1 b upper case mode; the high-order bit is masked off
\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 In addition, lower case is converted to upper case
\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 If the character is not printable, -1 is returned
\par 
\par \hich\af1\dbch\af31505\loch\f1 On input, TTUF_MODE_UC has an additional modifier, TTUF_MODE_KSR, which forces the high order \hich\af1\dbch\af31505\loch\f1 bit to be set rather than cleared.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The set of printable control characters is contained in the global bit-vector variable }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Each bit represents the character corresponding to the bit number (e.g., bit 0 represents NUL, bit 1 represents SOH, e\hich\af1\dbch\af31505\loch\f1 
tc.).  If a bit is set, the corresponding control character is considered printable.  It initially contains the following characters: BEL, BS, HT, LF, and CR.  The set may be manipulated with these routines:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_set_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 flag, char *cptr) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1  set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to the value pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ; return SCPE_2FARG if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is null or points to a null string, or SCPE_ARG if the value cannot be converted or does not contain at least CR and LF.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_show_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *st, DEVICE *dptr, UNIT *uptr
\hich\af1\dbch\af31505\loch\f1 , int32 flag, char *cptr) \hich\f1 \endash \loch\f1  output the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  value to the stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Note that the DEL character is always considered non-printable and will be suppressed in the UC and 7P modes.
\par 
\par {\*\bkmkstart _Toc356355659}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Multiplexer Emulation Library{\*\bkmkend _Toc356355659}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SIMH supports the use of multiple terminals.  All terminals except the console are accessed via Telnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1  or serial ports on the host machine}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  SIMH provides }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 three }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 supporting libraries for implementing multiple terminals: sim_tmxr.c (and its header file, si\hich\af1\dbch\af31505\loch\f1 m_tmxr.h), which provide OS-independent support routines for terminal multiplexers; }{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 sim_serial.c (and its header file sim_serial.h), which provide OS-dependent serial I/O routines; }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
and sim_sock.c (and its header file, sim_sock.h), which provide OS-dependen\hich\af1\dbch\af31505\loch\f1 t socket routines.  Sim_sock.c }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 and sim_serial.c are}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  implemented under Windows, VMS, UNIX, and MacOS.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Two basic data structures define the multiple terminals.  Individual lines are defined by an array of  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmln}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structures (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TMLN}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct tmln \{
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int\tab \tab \hich\af1\dbch\af31505\loch\f1 conn;\tab \tab \tab 
\tab /* line connected flag */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 SOCKET\tab sock;\tab \tab \tab \tab /* connection socket */

\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ipad;\tab \tab \tab \tab /* IP address */
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab master;\tab \tab \tab \tab /* line specific master socket */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *port;\tab \tab \tab \tab /* line specific listening port */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab sessions;\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* count of tcp connections received */
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab cnms;\tab \tab \tab \tab /* connect  time ms */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab tsta;\tab \tab \tab \tab /* Telnet state */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rcve;\tab \tab \tab \tab /* rcv enable */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab xmte;\tab \tab \tab \tab /* xmt enable */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab dstb;\tab \tab \tab \tab /* disable Tlnt bin */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab notelnet;\tab \tab \tab /* raw bina
\hich\af1\dbch\af31505\loch\f1 ry data (no telnet interpret) */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxbpr;\tab \tab \tab \tab /* rcv buf remove */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxbpi;\tab \tab \tab \tab /* rcv buf insert */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxcnt;\tab \tab \tab \tab /* rcv count */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbpr;\tab \tab \tab \tab /* xmt buf remove */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbpi;\tab \tab \tab \tab /* xmt buf insert */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txcnt;\tab \tab \tab \tab /* xmt count */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txdrp;\tab \tab \tab \tab /* xmt drop count */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1  \tab int32\tab \tab txbsz;\tab \tab \tab \tab /* xmt buffer size */

\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbfd;\tab \tab \tab \tab /* xmt buffered flag */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid2634434 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 t_bool}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 modem_control}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab 
\hich\af1\dbch\af31505\loch\f1 /* }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 line modem control support}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1  */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 modembits}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab 
\hich\af1\dbch\af31505\loch\f1 /* }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 modem bits which are set}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1  */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 FILE\tab \tab *txlog;\tab \tab \tab \tab /* xmt log file */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid3891160 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 FILEREF\tab *txlogref;\tab \tab \tab /* xmt log file reference */

\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *txlogname;\tab \tab \tab /* xmt log file name */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab rxb[TMXR_MAXBUF];\tab \tab /* rcv buffer */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab rbr[TMXR_MAXBUF];\tab \tab /* rcv break */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txb;}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid3891160 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 /* xmt buffer */
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 TMXR\tab \tab *mp;\tab \tab \tab \tab /* back pointer to mux */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *serconfig;\tab \tab \tab /* line config */
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid3891160 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 SERHANDLE\tab serport;\tab \tab \tab \tab /* serial port handle */

\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab \hich\af1\dbch\af31505\loch\f1 ser_connect_pending;\tab \tab 
/* serial connection notice pending */
\par \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab connecting;\tab \tab \tab /* Outgoing socket while connecting */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *destination;\tab \tab \tab /* Outgoing destination address:port */
\par \tab \hich\af1\dbch\af31505\loch\f1 UNIT\tab \tab *uptr;\tab \tab \tab \tab /* input polling unit -default to mp->uptr */
\par \tab \hich\af1\dbch\af31505\loch\f1 UNIT\tab \tab *\hich\af1\dbch\af31505\loch\f1 o_uptr;\tab \tab \tab \tab /* output polling unit \hich\f1 \endash \loch\f1 default to lp->uptr */
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 conn}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 connection }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 
\hich\af1\dbch\af31505\loch\f1 flag }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (0 = disconnected)
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid3891160 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3891160\charrsid3891160 \hich\af1\dbch\af31505\loch\f1 
sock}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \tab \hich\af1\dbch\af31505\loch\f1 connection socket
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid3806017 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \hich\af1\dbch\af31505\loch\f1 ipad\tab \tab IP address of remote end of connection
\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \tab \hich\af1\dbch\af31505\loch\f1 optional line specific listening socket
\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 port}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \tab \hich\af1\dbch\af31505\loch\f1 optional line specific listening port
\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017 \hich\af1\dbch\af31505\loch\f1 sessions}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \hich\af1\dbch\af31505\loch\f1 count of tcp connections received
\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 cnms}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \tab \hich\af1\dbch\af31505\loch\f1 connect time
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tsta}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 Telnet state
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rcve}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive enable flag (0 = disabled)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 xmte}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit flow control flag (0 = transmit disabled)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dstb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 Telnet bin mode disa\hich\af1\dbch\af31505\loch\f1 bled
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxbp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 r\tab \tab receive buffer remove pointer
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxbpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive buffer insert pointer
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxcnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive count
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txbpr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer remove pointer
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txbpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer insert pointer
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txcnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit count
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txlog}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to log file descriptor
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txlogname}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to log file name
\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 receive buffer
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rbr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive buffer break flags
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txb}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer
\par 
\par \hich\af1\dbch\af31505\loch\f1 The overall set of extra terminals is defined by the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TMXR}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct tmxr \{
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab lines;\tab \tab \tab \tab /* # lines */
\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \hich\af1\dbch\af31505\loch\f1 char}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 port;\tab \tab \tab \tab /* liste\hich\af1\dbch\af31505\loch\f1 ning port */
\par \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab master;\tab \tab \tab \tab /* master socket */
\par \tab \hich\af1\dbch\af31505\loch\f1 TMLN\tab \tab *ldsc;\tab \tab \tab \tab /* pointer to line descriptors */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab *lnorder;\tab \tab \tab /* line connection order */
\par \tab \hich\af1\dbch\af31505\loch\f1 DEVICE\tab *dptr;\tab \tab \tab \tab /* multiplexer device */
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 UNIT\tab \tab *uptr;\tab \tab \tab \tab /* polling unit (connection) */
\par \tab \hich\af1\dbch\af31505\loch\f1 char \tab \tab logfi\hich\af1\dbch\af31505\loch\f1 letmpl[FILENAMEMAX];\tab /* template logfile name */
\par \tab \hich\af1\dbch\af31505\loch\f1 int23\tab \tab buffered;\tab \tab \tab /* Buffered line behavior and buffer size*/
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab sessions;\tab \tab \tab /* count of tcp connections received */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab last_poll_time;\tab \tab \tab /* time of last connection poll */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab notelnet;\tab \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 /* default telnet capability for incoming connections */}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid3891160 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab modem_control;\tab \tab \tab /* multiplexer supports modem control behaviors */
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 number of lines (constant)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 port}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 master listening port (specified by ATTACH command)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 master listening socket (filled in by ATTACH command)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ldsc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 array of line descriptors
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab 
\hich\af1\dbch\af31505\loch\f1 array of line numbers in order of connection sequence, or NULL if user-defined connection order is n\hich\af1\dbch\af31505\loch\f1 ot required
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to the multiplexer\hich\f1 \rquote \loch\f1 
s DEVICE structure, or NULL if the device is to be derived from the UNIT passed to the attach call.
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid1264706 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid1264706 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 
\tab \hich\af1\dbch\af31505\loch\f1 the UNIT passed to the attach call.
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid7674256 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 logfiletmpl}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid1264706 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 template logfile name used to create names for per line log\hich\af1\dbch\af31505\loch\f1  filesl.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 buffered}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 
Buffered line behaviors enabled flag and the size of the line buffer.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid1264706 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 sessions}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid1264706 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 count of tcp connections received on the master socket}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 .
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid7674256 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 last_poll_time}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 time of last connection poll.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 notelnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 default telnet capability for tcp connections.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 mo\hich\af1\dbch\af31505\loch\f1 dem_control}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 
flag indicating that multiplexer supports full modem control behaviors.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid1264706 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 
\par 
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The number of elements in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ldsc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 
\ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  arrays must equal the value of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field.  Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to NULL if the connection order feature is not needed.  If t\hich\af1\dbch\af31505\loch\f1 he first element of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  array is \hich\f1 \endash \loch\f1 1, then the default ascending sequential connection order is used.  Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to NULL if the device should be derived from the unit passed to the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  call.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Library sim_tmxr.c provides the following routines\hich\af1\dbch\af31505\loch\f1  to support Telnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1  and Serial port}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -based terminals:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 tmxr_poll_conn}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp) \hich\f1 \endash \loch\f1  poll for a new connection to the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  If there is a new connection, the\hich\af1\dbch\af31505\loch\f1 
 routine resets all the line descriptor state (including receive enable) and returns the line number (index to line descriptor) for the new connection.  If there isn\hich\f1 \rquote \loch\f1 t a new connection, the routine returns \hich\f1 \endash 
\loch\f1 1.
\par 
\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_reset_ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp) \hich\f1 \endash \loch\f1 
 reset the lin\hich\af1\dbch\af31505\loch\f1 e described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  The connection is closed and all line descriptor state is reset.
\par 
\par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_getc_ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp) \hich\f1 \endash \loch\f1 
 return the next available character from the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  If a character is available, the return }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is:
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 (1 << TMXR_V_VA\hich\af2\dbch\af31505\loch\f2 LID) | character
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 If a BREAK occurred on the line, SCPE_BREAK will be ORed into the return variable.  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
If no character is available, the return }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is 0.
\par 
\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_poll_rx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp) \hich\f1 \endash \loch\f1 
 poll for input available on the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . 
\par 
\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_rqln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp) \hich\f1 \endash \loch\f1 
 return the number of characters in the receive queue of the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_putc_ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (TMLN *lp, int32 chr) \hich\f1 \endash \loch\f1  output character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 chr }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
to the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Possible errors are SCPE_LOST (connection lost) and SCP
\hich\af1\dbch\af31505\loch\f1 E_STALL (connection backlogged).
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_poll_tx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp) 
\hich\f1 \endash \loch\f1  poll for output complete on the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 .
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_tqln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp) \hich\f1 \endash \loch\f1 
 return the number of characters in the transmit queue of the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9308345 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9308345 
\hich\af1\dbch\af31505\loch\f1 tmxr_send_buff\hich\af1\dbch\af31505\loch\f1 ered_data}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp) \hich\f1 \endash \loch\f1  flush any buffered data for the line described by 
}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 .
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp, UNIT *uptr, char *cptr) \hich\f1 \endash \loch\f1  attach the port contained in character string }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_open_maste\hich\af1\dbch\af31505\loch\f1 r}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (TMXR *mp, char *cptr) \hich\f1 \endash \loch\f1  associate the port contained in character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  to the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  This routine is a subset of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (TMXR *mp, UNIT *uptr) \hich\f1 \endash \loch\f1  detach all connections for the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  and unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_close_master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp) \hich\f1 \endash \loch\f1 
 close the master port for the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  This routine is a subset of}{
\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  tmxr_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 .
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_ex}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1  stub examine routine, needed because the extra terminals are marked as attached; always returns an error.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_dep}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (t_value val, t_addr addr, UNIT *uptr, int32 sw) \hich\f1 \endash \loch\f1  stub deposit routine, needed because the extra terminals are marked as detached; \hich\af1\dbch\af31505\loch\f1 always returns an error.
\par }\pard \ltrpar\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \fi360\li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0\pararsid9308345 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9308345 
\hich\af1\dbch\af31505\loch\f1 tmxr_msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1  (SOCKET sock, char *msg) \hich\f1 \endash \loch\f1  output character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9308345 
\hich\af1\dbch\af31505\loch\f1 msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1  to socket sock.
\par 
\par }\pard \ltrpar\ql \fi360\li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 tmxr_linemsg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp, char *msg) \hich\f1 \endash \loch\f1  output character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to line }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 .
\par 
\par }\pard \ltrpar\ql \fi360\li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0\pararsid2634434 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid2634434 
\hich\af1\dbch\af31505\loch\f1 tmxr_linemsg}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 f}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp, }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 const *fmt, ,,,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 ) \hich\f1 \endash \loch\f1  output }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 
\hich\af1\dbch\af31505\loch\f1 formatted }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1  to line }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 .
\par 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_fconns}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, TMLN *lp, int32 ln) \hich\f1 \endash \loch\f1  output conn\hich\af1\dbch\af31505\loch\f1 ection status to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  for the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  If }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is >= 0, preface the output with the specified line number.
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_fstats}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *st, TMLN *lp, int32 ln) \hich\f1 
\endash \loch\f1  output connection statistics to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  for the line described by }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is\hich\af1\dbch\af31505\loch\f1  >= 0, preface the output with the specified line number.
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 tstat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid9308345\charrsid2698330 \hich\af1\dbch\af31505\loch\f1 tmxr_set_log}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 
\hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 val, char *cptr, void *mp) \hich\f1 \endash \loch\f1  enable logging of a line of the multipleser described by mp to the filename pointed to by cptr.  If uptr is NULL, then val indicate
\hich\af1\dbch\af31505\loch\f1 s the line number; otherwise, the unit number within the associated device implies the line number.  This function may be used as an MTAB validation routine.
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid2698330 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1 tstat }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\b\f1\insrsid2698330\charrsid5979563 \hich\af1\dbch\af31505\loch\f1 tmxr_set_}{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1 no}{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid2698330\charrsid5979563 
\hich\af1\dbch\af31505\loch\f1 log}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 val, char *cptr, void *mp) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 
 disable logging of a line of the multipleser described by mp to the filename pointed to by cptr.  If uptr is NULL, then val indicates the line number; otherwise, the unit number within the associated device implies the line number.  This function may be 
\hich\af1\dbch\af31505\loch\f1 u\hich\af1\dbch\af31505\loch\f1 sed as an MTAB validation routine.
\par 
\par \hich\af1\dbch\af31505\loch\f1 tstat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid2698330\charrsid2698330 \hich\af1\dbch\af31505\loch\f1 tmxr_show_log}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *mp) \hich\f1 \endash \loch\f1  outputs the logging status of a line of the multiplexer described by mp to stream st.  If uptr is NULL, then val indicates the line number; otherwise, the
\hich\af1\dbch\af31505\loch\f1  unit number within the associated device implies the line number.  This function may be used as an MTAB display routine.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid2698330 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 tmxr_dscln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 val, char *cptr, void *mp) \hich\f1 \endash \loch\f1  parse the string pointed to by }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  for a decimal line number.  If \hich\af1\dbch\af31505\loch\f1 
the line number is valid, disconnect the specified line in the terminal multiplexer described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .  The calling sequence allows }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_dscln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 to be used as an MTAB processing routine.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1   A line connected via a tcp session will be disconnected, a line connecte\hich\af1\dbch\af31505\loch\f1 
d to a serial port will be closed if the sim_switches \hich\f1 \endash \loch\f1 C flag is enabled when the routine is called, otherwise a serial port will have DTR dropped for 500ms and raised again.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 

\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_set_lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  set th\hich\af1\dbch\af31505\loch\f1 e line connection order array associated with the TMXR structure pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The string pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is parsed for a semicolon-delimited list of ranges.  Ranges are of the form:
\par 
\par }\pard \ltrpar\ql \fi-2160\li3600\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin3600\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1-line2\tab ascending sequence from }{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 
\b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2  to }{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line2}{\rtlch\fcs1 \af2 
\ltrch\fcs0 \f2\insrsid4550150 
\par \hich\af2\dbch\af31505\loch\f2 line1/lengt\hich\af2\dbch\af31505\loch\f2 h\tab ascending sequence from }{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 
\hich\af2\dbch\af31505\loch\f2  to }{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 +}{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 
\b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 length}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 -1
\par \hich\af2\dbch\af31505\loch\f2 ALL\tab ascending sequence of all lines defined by the multiplexer
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The line order array must provide an int32 element for each line.  The calling sequence allows }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_set_lnorder}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to be used as an MTAB processi\hich\af1\dbch\af31505\loch\f1 ng routine.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  output the line connection order associated multiplexer (TMXR *) }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af0 
\ltrch\fcs0 \insrsid4550150 \hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The order is rendered as a semicolon-delimited list of ranges.  The calling sequence \hich\af1\dbch\af31505\loch\f1 allows }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 tmxr_show_lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to be used as an MTAB processing routine.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  outputs the summary status of the multiplexer (TMXR *) }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_cstat}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  outputs either the connections (val = 1) or the statistics (val = 0) of the multiplexer (TMXR *) }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 . Also checks for multiplexer not attached, or all lines disconnected.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_line\hich\af1\dbch\af31505\loch\f1 s}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  outputs the number of lines in the terminal multiplexer (TMXR *) I to stream I.
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 
\par }\pard \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid7674256 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid7674256 
\hich\af1\dbch\af31505\loch\f1 tmxr_set_modem_control_passthru}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp) \hich\f1 \endash \loch\f1  Enables modem control passthru behaviors, and disables internal manipulat
\hich\af1\dbch\af31505\loch\f1 ion of DTR (&RTS) by tmxr apis.  Enables the tmxr_set_get_modem_bits and tmxr_set_config_line apis.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 tmxr_clear_modem_control_passthru}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp) \hich\f1 
\endash \loch\f1  Disables modem control passthru behaviors, and enables internal manipulation of DTR (&RTS) by tmxr apis.  Disables the tmxr_set_get\hich\af1\dbch\af31505\loch\f1 _modem_bits and tmxr_set_config_line apis.
\par 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid9462171\charrsid9462171 \hich\af1\dbch\af31505\loch\f1 tmxr_set_get_modem_bits}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 
\hich\af1\dbch\af31505\loch\f1  (TMLN *lp, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits) \hich\f1 \endash \loch\f1  For a line connected to a serial port on a TMXR device with modem_control_passthru enabled, then the bits_
\hich\af1\dbch\af31505\loch\f1 to_set and/or bits_to_clear (DTR and RTS) are changed and if incoming_bits is not NULL, then the current modem bits are returned (DCD,RNG,CTS, DSR).}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid9462171\charrsid9462171 \hich\af1\dbch\af31505\loch\f1 tmxr_set_config_line}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 
 (TMLN *lp, char *config) \hich\f1 \endash \loch\f1  sets the line configuration (speed, parity, charact\hich\af1\dbch\af31505\loch\f1 er size, stopbits) on a serial port.  Config is a string of the form: 9600-8N1.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid9462171\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 tmxr_set_line_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 
 (TMXR *mp, int line, UNIT *uptr) }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid3806017 \loch\af1\dbch\af31505\hich\f1 \endash }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid3806017 
\hich\af1\dbch\af31505\loch\f1 Declare which unit polls for input on a given line (only needed if the input polling unit is different than the un\hich\af1\dbch\af31505\loch\f1 it provided when the multiplexer was attached.}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid9462171 
\par }\pard \ltrpar\s21\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid3806017 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid2698330 
\par }\pard \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid8129972 
\par }\pard \ltrpar\s21\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid8129972 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid8129972 \hich\af1\dbch\af31505\loch\f1 
The OS dependent serial I/O and socket routines should not need to be accessed by the terminal simulators.
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par {\*\bkmkstart _Toc356355660}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Magnetic Tape Emulation Library{\*\bkmkend _Toc356355660}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 \hich\f1 SIMH supports the use of emulated magnetic tapes.  Magnetic tapes are emulated as disk files containing both data records and metadata markers; the format is fully described in the paper \'93\loch\f1 \hich\f1 
SIMH Magtape Representation and Handling\'94\loch\f1 .  SIMH provides a support\hich\af1\dbch\af31505\loch\f1 i\hich\af1\dbch\af31505\loch\f1 
ng library, sim_tape.c (and its header file, sim_tape.h), that abstracts handling of magnetic tapes.  This allows support for multiple tape formats, without change to magnetic device simulators.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The magtape library does not require any special data struct\hich\af1\dbch\af31505\loch\f1 ures.  However, it does define some additional unit flags:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 MTUF_WLK\tab \tab unit is write locked
\par 
\par \hich\af1\dbch\af31505\loch\f1 If magtape simulators need to define private unit flags, those flags should begin at bit number MTUF_V_UF instead of UNIT_V_UF.  The magtape library maintains the \hich\af1\dbch\af31505\loch\f1 
current magtape position in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pos}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Library sim_tape.c provides the following routines to support emulated magnetic tapes:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_tape_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, char *cptr) \hich\f1 \endash \loch\f1  Attach tape unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 uptr }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Tape 
\par \hich\af1\dbch\af31505\loch\f1 Simulator\hich\af1\dbch\af31505\loch\f1 s should call this routine, rather than the standard attach_unit routine, to allow for future expansion of format support.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Detach tape unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  from its current file.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_set_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 val, 
\hich\af1\dbch\af31505\loch\f1 char *cptr, void *desc) \hich\f1 \endash \loch\f1  Set the tape format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  to the format specified by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  Write the tape format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_sta\hich\af1\dbch\af31505\loch\f1 t }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  Set the tape capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  to the capacity, in MB, specified by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1  Write the capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_rdrecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, uint8 *buf, t_mtrlnt *tbc, t_mtrlnt max) \hich\f1 \endash \loch\f1  Forward read the next record on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  of size }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Return the actual record size in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 .
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_rdrecr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, uint8 *buf, t_mtrlnt *tbc, t_mtrlnt max) \hich\f1 \endash \loch\f1  Reverse read the next record on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  of size }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Return the actual record size in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Note that the record is \hich\af1\dbch\af31505\loch\f1 
returned in forward order, that is, byte 0 of the record is stored in buf[0], and so on.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrrecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, uint8 buf, t_mtrlnt tbc) \hich\f1 \endash \loch\f1  Write buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 of size }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  as the next record on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape sprecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, t_m
\hich\af1\dbch\af31505\loch\f1 trlnt *tbc) \hich\f1 \endash \loch\f1  Space unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 forward one record.  The size of the record is returned in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_sprecr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, t_mtrlnt *tbc) 
\hich\f1 \endash \loch\f1  Space unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 reverse one record.  The size of the record is returned in tbc.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrtmk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT
\hich\af1\dbch\af31505\loch\f1  *uptr) \hich\f1 \endash \loch\f1  Write a tape mark on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wreom}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Write an end-of-medium marker on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (this effectively erases the rest of the tape).
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrgap}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, uint32 gaplen, uint32 bpi) \hich\f1 \endash \loch\f1  Write an erase gap o\hich\af1\dbch\af31505\loch\f1 n unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 gaplen}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 tenths of an inch in length at a tape density of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 bpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  bits per inch.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_rewind}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Rewind unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  This operation succeeds whether or not the unit is attached to a file.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\hich\af1\dbch\af31505\loch\f1  Reset unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  This routine should be called when a tape unit is reset.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_bot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Return TRUE if unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is at beginning-of-tape.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape wrp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Return TRUE if unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is write-protected.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_eot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Return TRUE if unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 has exceed the capacity specified of the specified unit (kept in uptr->capac).
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Sim_tape_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_tape_detach, sim_tape_set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
sim_tape_show_fmt, sim_tape_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_capac}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  return s\hich\af1\dbch\af31505\loch\f1 
tandard SCP status codes; the other magtape library routines return return private codes for success and failure.  The currently defined magtape status codes are:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_OK\tab \tab operation successful
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_UNATT\tab \tab unit is not attached to a file
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_FMT\tab \tab \hich\af1\dbch\af31505\loch\f1 unit specifies an unsupported tape file format
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_IOERR\tab \tab host operating system I/O error during operation
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_INVRL\tab \tab invalid record length (exceeds maximum allowed)
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_RECE\tab \tab record header contains error flag
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_TMK\tab \tab tape mark encountered
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_B\hich\af1\dbch\af31505\loch\f1 OT\tab \tab beginning of tape encountered during reverse operation
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_EOM\tab \tab end of medium encountered
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_WRP\tab \tab write protected unit during write operation
\par 
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Sim_tape_set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_tape_show_fmt, sim_tape_set_capac, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  should be referenced by\hich\af1\dbch\af31505\loch\f1  an entry in the tape device\hich\f1 \rquote \loch\f1 s modifier list, as follows:
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 MTAB tape_mod[] = \{
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  MTAB_XTD|MTAB_VDV, 0, \'93\loch\f2 \hich\f2 FORMAT\'94\loch\f2 
\hich\f2 , \'93\loch\f2 \hich\f2 FORMAT\'94,
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2   \tab   &sim_tape_set_fmt, &sim_tape_show_fmt, NULL \},
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  MTAB_XTD|MTAB_VUN, 0, \'93\loch\f2 \hich\f2 CAPACITY\'94\loch\f2 
\hich\f2 , \'93\loch\f2 \hich\f2 CAPACITY\'94,
\par }\pard \ltrpar\ql \li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2   &sim_tape_set_capac, &sim_tap\hich\af2\dbch\af31505\loch\f2 e_show_capac, NULL \}
\hich\f2 , \'85
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \}\hich\af2\dbch\af31505\loch\f2 ;
\par {\*\bkmkstart _Toc356355661}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 6.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0\pararsid9973523 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9973523 \hich\af1\dbch\af31505\loch\f1 Disk Emulation Library{\*\bkmkend _Toc356355661}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9973523 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid9973523 
\par \hich\af1\dbch\af31505\loch\f1 \hich\f1 SIMH supports the use of disk drives.  Disk drives as disk files containing both data records and metadata markers; the format is fully described in the paper \'93\loch\f1 SIMH Magtape Re
\hich\af1\dbch\af31505\loch\f1 \hich\f1 presentation and Handling\'94\loch\f1 
.  SIMH provides a supporting library, sim_disk.c (and its header file, sim_disk.h), that abstracts handling of disk drives tapes.  This allows support for disk formats, without change to magnetic device simulators.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The disk libr\hich\af1\dbch\af31505\loch\f1 ary does not require any special data structures.  However, it does define some additional unit flags:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 DKUF_WLK\tab \tab unit is write locked
\par 
\par \hich\af1\dbch\af31505\loch\f1 If magtape simulators need to define private unit flags, those flags should begin at bit\hich\af1\dbch\af31505\loch\f1  number DKUF_V_UF instead of UNIT_V_UF.  The disk library maintains the current magtape position in the }
{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 pos}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  field of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 
\hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  structure.
\par \hich\af1\dbch\af31505\loch\f1 Library sim_tape.c provides the following routines to support emulated magnetic tapes:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 
\hich\af1\dbch\af31505\loch\f1 sim_disk_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  (UNIT *u\hich\af1\dbch\af31505\loch\f1 ptr, char *cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 
\hich\af1\dbch\af31505\loch\f1 , s}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 
ize_t sector_size, size_t xfer_element_size, t_bool dontautosize, uint32 debugbit, const char *drivetype, uint32 pdp11_tracksize, int completion_delay) \hich\f1 \endash \loch\f1  Attach disk unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 
\hich\af1\dbch\af31505\loch\f1 uptr }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 to file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 .  Disk Simulators should call this routine, rathe\hich\af1\dbch\af31505\loch\f1 r than the standard attach_unit routine, 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 
\hich\af1\dbch\af31505\loch\f1 _detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash \loch\f1  Detach }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 disk}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 
\hich\af1\dbch\af31505\loch\f1  from its current file.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _set_fmt}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  Set the }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 
 to the format specifi\hich\af1\dbch\af31505\loch\f1 ed by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 sim_}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _show_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  (FILE *st, UNIT *uptr, int32 v}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 
al, void *desc) \hich\f1 \endash \loch\f1  Write the disk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 .

\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _set_capac}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 val, char *}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 cptr, void *desc) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1  Set the disk}
{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 
\hich\af1\dbch\af31505\loch\f1  to the capacity, in MB, specified by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _show_capac}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  Write the capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr}
{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 
.
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9973523 
\par }\pard \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid11167734 
\hich\af1\dbch\af31505\loch\f1 sim_disk_rds\hich\af1\dbch\af31505\loch\f1 ect}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectsread, , t_seccnt *sectstoread) \hich\f1 
\endash \loch\f1  Read up to sectstoread sectors from sector number lba on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 
 into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 .  Return the number of sectors read in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sectsread}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 .
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_disk_rdsect_a}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 
\hich\af1\dbch\af31505\loch\f1  (UNIT *up\hich\af1\dbch\af31505\loch\f1 tr, t_lba lba, uint8 *buf, t_seccnt *sectsread, , t_seccnt *sectstoread}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 , DISK_PCALLBACK callback}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 ) \hich\f1 \endash \loch\f1  Read up to sectstoread sectors from sector number lba on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 
uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1  into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid15957281 
\hich\af1\dbch\af31505\loch\f1  asynchronously}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 .  Return the number of sectors read in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 
sectsread}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 , and call\hich\af1\dbch\af31505\loch\f1  callback routine on completion.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_wrsect}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 
\hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectswritten, , t_seccnt *sectstowrite) \hich\f1 \endash \loch\f1 
 Write sectstowrite sectors from buffer buf to disk sector number lba on unit uptr.  Return the number of sector\hich\af1\dbch\af31505\loch\f1 s written in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sectswritten}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 .
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid15957281 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_wrsect_a}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 
\hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectswritten, , t_seccnt *sectstowrite, DISK_PCALLBACK callback) \hich\f1 \endash \loch\f1  Write sectstowrite sectors from buffer buf to disk sector number lba on unit }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 
asynchronously}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 .  Return the number of sectors written in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sectswritten}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 , and call callback routine on completion.
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid15957281 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 
\hich\af1\dbch\af31505\loch\f1 disk_unload}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash \loch\f1  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 
Unload or detach a disk as needed.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_set_asynch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 
\hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int latency) \hich\f1 \endash \loch\f1  Enable asynchr\hich\af1\dbch\af31505\loch\f1 onouos operation for I/O to disk unit uptr.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_clr_asynch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int latency) 
\hich\f1 \endash \loch\f1  Disable asynchronouos operation for I/O to disk unit uptr.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash \loch\f1 
 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid13897431 \hich\af1\dbch\af31505\loch\f1 Reset unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid13897431 
\hich\af1\dbch\af31505\loch\f1 .  This routine should be called when a tape\hich\af1\dbch\af31505\loch\f1  unit is reset.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_isavailable }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Check to see if disk is available for I/O, return TRUE if so.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_isavailable_a }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 
(UNIT *uptr, DISK_PCALLBACK callback) \hich\f1 \endash \loch\f1  Check to see if disk is available for I/O asynchronously.  Retu\hich\af1\dbch\af31505\loch\f1 rn }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid13897431 \hich\af1\dbch\af31505\loch\f1 TRUE}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1  if so.
\par 
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid13897431 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid15957281 \hich\af0\dbch\af31505\loch\f0 t_}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid13897431 \hich\af0\dbch\af31505\loch\f0 bool}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid15957281 \hich\af0\dbch\af31505\loch\f0  }{
\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid15957281 \hich\af0\dbch\af31505\loch\f0 sim_disk_}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid13897431 \hich\af0\dbch\af31505\loch\f0 wrp}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid15957281 
\hich\af0\dbch\af31505\loch\f0  (UNIT *uptr) \hich\f0 \endash \loch\f0  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 Return TRUE if unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid13897431 
\hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1  is write-protected.
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 
\par }\pard \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid13897431 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid13897431 \hich\af1\dbch\af31505\loch\f1 t_addr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid13897431 
\hich\af1\dbch\af31505\loch\f1 sim_disk_size}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid13897431 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash \loch\f1  get disk size
\par 
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9973523 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 
\ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 Sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 
, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 sim_disk_detach, sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 sim_disk_show_fmt, sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 
_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 , and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 sim_tape_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 
\hich\af1\dbch\af31505\loch\f1 _capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  return standard SCP status codes; the other }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 disk}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  library routines return return private codes for success and failure.  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 
Success status is DKSE_OK and any other value is an error.  Errno usually will have the appropriate error code}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 :
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 DKSE_OK\tab \tab operat\hich\af1\dbch\af31505\loch\f1 ion successful
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 Sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 
\hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 sim_}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _show_fmt, sim_}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 
_set_capac, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 sim_}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 
\hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  should be referenced by an entry in the }
{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1  device\hich\f1 \rquote \loch\f1 s modifier list, as follows:
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \tab \hich\af2\dbch\af31505\loch\f2 MTAB tape_mod[] = \{
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  MTAB_XTD|MTAB_VDV, 0, \'93\loch\f2 \hich\f2 FORMAT
\'94\loch\f2 \hich\f2 , \'93\loch\f2 \hich\f2 FORMAT\'94,
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \tab \hich\af2\dbch\af31505\loch\f2   \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid13897431 
\hich\af2\dbch\af31505\loch\f2   &sim_\hich\af2\dbch\af31505\loch\f2 disk}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \hich\af2\dbch\af31505\loch\f2 _set_fmt, &sim_}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid13897431 \hich\af2\dbch\af31505\loch\f2 disk
}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \hich\af2\dbch\af31505\loch\f2 _show_fmt, NULL \},
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  MTAB_XTD|MTAB_VUN, 0, \'93\loch\f2 \hich\f2 CAPACITY
\'94\loch\f2 \hich\f2 , \'93\loch\f2 \hich\f2 CAPACITY\'94,
\par }\pard \ltrpar\ql \li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid13897431 \hich\af2\dbch\af31505\loch\f2   &sim_disk}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 
\hich\af2\dbch\af31505\loch\f2 _set_capac, &sim_}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid13897431 \hich\af2\dbch\af31505\loch\f2 disk}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \hich\af2\dbch\af31505\loch\f2 _show_capac, NULL \}\hich\f2 , \'85

\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \}\hich\af2\dbch\af31505\loch\f2 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9973523 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 
\par {\*\bkmkstart _Toc356355662}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.5\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Breakpoint Support{\*\bkmkend _Toc356355662}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP provides underlying mechanisms to track multiple brea\hich\af1\dbch\af31505\loch\f1 kpoints of different types.  Most VM\hich\f1 \rquote \loch\f1 
s implement at least instruction execution breakpoints (type E); but a VM might also allow for break on read (type R), write (type W), and so on.  Up to 26 different breakpoint types, identified by the letters A throug\hich\af1\dbch\af31505\loch\f1 h
\hich\af1\dbch\af31505\loch\f1  Z, are supported.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The VM interface to the breakpoint package consists of three variables and one subroutine:
\par 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_types}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  \hich\f1 \endash \loch\f1 
 initialized by the VM (usually in the CPU reset routine) to a mask of all supported breakpoints.
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_dflt}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  \hich\f1 \endash \loch\f1  initialized by\hich\af1\dbch\af31505\loch\f1  the VM to the mask for the default breakpoint type.
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  \hich\f1 \endash \loch\f1  maintained by SCP, providing a bit mask summary of whether any breakpoints of a particular type have been defined.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If the VM only implements one type of breakpoint, then }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  is \hich\af1\dbch\af31505\loch\f1 non-zero if any breakpoints are set.
\par 
\par \hich\af1\dbch\af31505\loch\f1 To test whether a breakpoint of particular type is set for an address, the VM calls
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uint32l }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_brk_test}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (t_addr addr, int32 typ) \hich\f1 \endash \loch\f1  test to see if a breakpoint of type }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 typ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is set for location }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ; returns 0 if no, and a bit mask of all breakpoints that match typ if yes
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Because }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_test}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 can be a lengthy procedure, it is usually prefaced with a test of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :
\par 
\par \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 if (sim_brk_summ && sim_brk_test (PC, SWMASK (\hich\f2 \lquote \loch\f2 E\hich\f2 \rquote \loch\f2 ))) \{
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 <execution break> \}
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 T\hich\af1\dbch\af31505\loch\f1 
o accommodate more complex breakpoint schemes, SCP implements a concept of breakpoint spaces.  Each breakpoint space is an orthogonal collection of breakpoints that are tracked independently.  For example, in a symmetric multiprocessing simulation, breakp
\hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 
int spaces could be assigned to each CPU to distinguish E (execution) breakpoints for different processors.  SCP supports up to 64 breakpoint spaces; the space is specified by bits <31:26> of the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 typ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  argument to }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_test}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  By default, there is only one\hich\af1\dbch\af31505\loch\f1  breakpoint space (space 0).
\par 
\par }{\*\themedata 504b030414000600080000002100e9de0fbfff0000001c020000130000005b436f6e74656e745f54797065735d2e786d6cac91cb4ec3301045f748fc83e52d4a
9cb2400825e982c78ec7a27cc0c8992416c9d8b2a755fbf74cd25442a820166c2cd933f79e3be372bd1f07b5c3989ca74aaff2422b24eb1b475da5df374fd9ad
5689811a183c61a50f98f4babebc2837878049899a52a57be670674cb23d8e90721f90a4d2fa3802cb35762680fd800ecd7551dc18eb899138e3c943d7e503b6
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