doc/simh.doc

{\rtf1\adeflang1025\ansi\ansicpg1252\uc1\adeff0\deff0\stshfdbch31505\stshfloch31506\stshfhich31506\stshfbi31507\deflang1033\deflangfe1033\themelang1033\themelangfe0\themelangcs0{\fonttbl{\f0\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f1\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604020202020204}Arial;}
{\f2\fbidi \fmodern\fcharset0\fprq1{\*\panose 02070309020205020404}Courier New;}{\f3\fbidi \froman\fcharset2\fprq2{\*\panose 05050102010706020507}Symbol;}{\f10\fbidi \fnil\fcharset2\fprq2{\*\panose 05000000000000000000}Wingdings;}
{\f11\fbidi \fmodern\fcharset128\fprq1{\*\panose 02020609040205080304}MS Mincho{\*\falt MS ??};}{\f34\fbidi \froman\fcharset1\fprq2{\*\panose 02040503050406030204}Cambria Math;}{\f38\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604030504040204}Tahoma;}
{\f39\fbidi \fmodern\fcharset128\fprq1{\*\panose 00000000000000000000}@MS Mincho;}{\flomajor\f31500\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}
{\fdbmajor\f31501\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\fhimajor\f31502\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria;}
{\fbimajor\f31503\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\flominor\f31504\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}
{\fdbminor\f31505\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\fhiminor\f31506\fbidi \fswiss\fcharset0\fprq2{\*\panose 020f0502020204030204}Calibri;}
{\fbiminor\f31507\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f40\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\f41\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
{\f43\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\f44\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\f45\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\f46\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
{\f47\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\f48\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\f50\fbidi \fswiss\fcharset238\fprq2 Arial CE;}{\f51\fbidi \fswiss\fcharset204\fprq2 Arial Cyr;}
{\f53\fbidi \fswiss\fcharset161\fprq2 Arial Greek;}{\f54\fbidi \fswiss\fcharset162\fprq2 Arial Tur;}{\f55\fbidi \fswiss\fcharset177\fprq2 Arial (Hebrew);}{\f56\fbidi \fswiss\fcharset178\fprq2 Arial (Arabic);}
{\f57\fbidi \fswiss\fcharset186\fprq2 Arial Baltic;}{\f58\fbidi \fswiss\fcharset163\fprq2 Arial (Vietnamese);}{\f60\fbidi \fmodern\fcharset238\fprq1 Courier New CE;}{\f61\fbidi \fmodern\fcharset204\fprq1 Courier New Cyr;}
{\f63\fbidi \fmodern\fcharset161\fprq1 Courier New Greek;}{\f64\fbidi \fmodern\fcharset162\fprq1 Courier New Tur;}{\f65\fbidi \fmodern\fcharset177\fprq1 Courier New (Hebrew);}{\f66\fbidi \fmodern\fcharset178\fprq1 Courier New (Arabic);}
{\f67\fbidi \fmodern\fcharset186\fprq1 Courier New Baltic;}{\f68\fbidi \fmodern\fcharset163\fprq1 Courier New (Vietnamese);}{\f152\fbidi \fmodern\fcharset0\fprq1 MS Mincho Western{\*\falt MS ??};}
{\f150\fbidi \fmodern\fcharset238\fprq1 MS Mincho CE{\*\falt MS ??};}{\f151\fbidi \fmodern\fcharset204\fprq1 MS Mincho Cyr{\*\falt MS ??};}{\f153\fbidi \fmodern\fcharset161\fprq1 MS Mincho Greek{\*\falt MS ??};}
{\f154\fbidi \fmodern\fcharset162\fprq1 MS Mincho Tur{\*\falt MS ??};}{\f157\fbidi \fmodern\fcharset186\fprq1 MS Mincho Baltic{\*\falt MS ??};}{\f420\fbidi \fswiss\fcharset238\fprq2 Tahoma CE;}{\f421\fbidi \fswiss\fcharset204\fprq2 Tahoma Cyr;}
{\f423\fbidi \fswiss\fcharset161\fprq2 Tahoma Greek;}{\f424\fbidi \fswiss\fcharset162\fprq2 Tahoma Tur;}{\f425\fbidi \fswiss\fcharset177\fprq2 Tahoma (Hebrew);}{\f426\fbidi \fswiss\fcharset178\fprq2 Tahoma (Arabic);}
{\f427\fbidi \fswiss\fcharset186\fprq2 Tahoma Baltic;}{\f428\fbidi \fswiss\fcharset163\fprq2 Tahoma (Vietnamese);}{\f429\fbidi \fswiss\fcharset222\fprq2 Tahoma (Thai);}{\f432\fbidi \fmodern\fcharset0\fprq1 @MS Mincho Western;}
{\f430\fbidi \fmodern\fcharset238\fprq1 @MS Mincho CE;}{\f431\fbidi \fmodern\fcharset204\fprq1 @MS Mincho Cyr;}{\f433\fbidi \fmodern\fcharset161\fprq1 @MS Mincho Greek;}{\f434\fbidi \fmodern\fcharset162\fprq1 @MS Mincho Tur;}
{\f437\fbidi \fmodern\fcharset186\fprq1 @MS Mincho Baltic;}{\flomajor\f31508\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\flomajor\f31509\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
{\flomajor\f31511\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\flomajor\f31512\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\flomajor\f31513\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}
{\flomajor\f31514\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\flomajor\f31515\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\flomajor\f31516\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}
{\fdbmajor\f31518\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fdbmajor\f31519\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fdbmajor\f31521\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}
{\fdbmajor\f31522\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\fdbmajor\f31523\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fdbmajor\f31524\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
{\fdbmajor\f31525\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fdbmajor\f31526\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fhimajor\f31528\fbidi \froman\fcharset238\fprq2 Cambria CE;}
{\fhimajor\f31529\fbidi \froman\fcharset204\fprq2 Cambria Cyr;}{\fhimajor\f31531\fbidi \froman\fcharset161\fprq2 Cambria Greek;}{\fhimajor\f31532\fbidi \froman\fcharset162\fprq2 Cambria Tur;}
{\fhimajor\f31535\fbidi \froman\fcharset186\fprq2 Cambria Baltic;}{\fhimajor\f31536\fbidi \froman\fcharset163\fprq2 Cambria (Vietnamese);}{\fbimajor\f31538\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}
{\fbimajor\f31539\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fbimajor\f31541\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fbimajor\f31542\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}
{\fbimajor\f31543\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fbimajor\f31544\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbimajor\f31545\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}
{\fbimajor\f31546\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\flominor\f31548\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\flominor\f31549\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
{\flominor\f31551\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\flominor\f31552\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\flominor\f31553\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}
{\flominor\f31554\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\flominor\f31555\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\flominor\f31556\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}
{\fdbminor\f31558\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fdbminor\f31559\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fdbminor\f31561\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}
{\fdbminor\f31562\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\fdbminor\f31563\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fdbminor\f31564\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
{\fdbminor\f31565\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fdbminor\f31566\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fhiminor\f31568\fbidi \fswiss\fcharset238\fprq2 Calibri CE;}
{\fhiminor\f31569\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}{\fhiminor\f31571\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;}{\fhiminor\f31572\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;}
{\fhiminor\f31575\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}{\fhiminor\f31576\fbidi \fswiss\fcharset163\fprq2 Calibri (Vietnamese);}{\fbiminor\f31578\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}
{\fbiminor\f31579\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fbiminor\f31581\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fbiminor\f31582\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}
{\fbiminor\f31583\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fbiminor\f31584\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbiminor\f31585\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}
{\fbiminor\f31586\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}}{\colortbl;\red0\green0\blue0;\red0\green0\blue255;\red0\green255\blue255;\red0\green255\blue0;\red255\green0\blue255;\red255\green0\blue0;\red255\green255\blue0;
\red255\green255\blue255;\red0\green0\blue128;\red0\green128\blue128;\red0\green128\blue0;\red128\green0\blue128;\red128\green0\blue0;\red128\green128\blue0;\red128\green128\blue128;\red192\green192\blue192;}{\*\defchp 
\fs22\loch\af31506\hich\af31506\dbch\af31505 }{\*\defpap \ql \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 }\noqfpromote {\stylesheet{
\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \snext0 \sqformat \spriority0 Normal;}{
\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 
\b\fs28\lang1033\langfe1033\kerning28\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \slink15 \sqformat heading 1;}{\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \slink16 \sqformat heading 2;}{\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 
\fs24\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \slink17 \sqformat heading 3;}{\*\cs10 \additive Default Paragraph Font;}{\*
\ts11\tsrowd\trftsWidthB3\trpaddl108\trpaddr108\trpaddfl3\trpaddft3\trpaddfb3\trpaddfr3\tblind0\tblindtype3\tsvertalt\tsbrdrt\tsbrdrl\tsbrdrb\tsbrdrr\tsbrdrdgl\tsbrdrdgr\tsbrdrh\tsbrdrv \ql \li0\ri0\sa200\sl276\slmult1
\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af31507\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\loch\f31506\hich\af31506\dbch\af31505\cgrid\langnp1033\langfenp1033 \snext11 \ssemihidden \sunhideused 
Normal Table;}{\*\cs15 \additive \rtlch\fcs1 \ab\af31503\afs32 \ltrch\fcs0 \b\fs32\kerning32\loch\f31502\hich\af31502\dbch\af31501 \sbasedon10 \slink1 \slocked \spriority9 Heading 1 Char;}{\*\cs16 \additive \rtlch\fcs1 \ab\ai\af31503\afs28 \ltrch\fcs0 
\b\i\fs28\loch\f31502\hich\af31502\dbch\af31501 \sbasedon10 \slink2 \slocked \ssemihidden \spriority9 Heading 2 Char;}{\*\cs17 \additive \rtlch\fcs1 \ab\af31503\afs26 \ltrch\fcs0 \b\fs26\loch\f31502\hich\af31502\dbch\af31501 
\sbasedon10 \slink3 \slocked \ssemihidden \spriority9 Heading 3 Char;}{\*\cs18 \additive \rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b \sbasedon10 \sqformat Strong;}{\s19\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 
\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\fs20\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext19 \slink20 Body Text;}{\*\cs20 \additive \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f0\fs20 
\sbasedon10 \slink19 \slocked \ssemihidden Body Text Char;}{\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 
\fs20\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext21 \slink22 Body Text 2;}{\*\cs22 \additive \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f0\fs20 \sbasedon10 \slink21 \slocked \ssemihidden Body Text 2 Char;}{
\s23\ql \li0\ri0\sb120\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd 
toc 1;}{\s24\ql \li200\ri0\sb120\widctlpar\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 \b\fs22\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \sautoupd toc 2;}{\s25\ql \li400\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \sautoupd toc 3;}{\s26\ql \li600\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin600\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \sautoupd toc 4;}{\s27\ql \li800\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin800\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \sautoupd toc 5;}{\s28\ql \li1000\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1000\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \sautoupd toc 6;}{\s29\ql \li1200\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \sautoupd toc 7;}{\s30\ql \li1400\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \sautoupd toc 8;}{\s31\ql \li1600\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1600\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext0 \sautoupd toc 9;}{\s32\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \cbpat9 \rtlch\fcs1 \af38\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f38\hich\af38\dbch\af31505\cgrid\langnp1033\langfenp1033 
\sbasedon0 \snext32 \slink33 Document Map;}{\*\cs33 \additive \rtlch\fcs1 \af38\afs16 \ltrch\fcs0 \f38\fs16 \sbasedon10 \slink32 \slocked \ssemihidden Document Map Char;}{\s34\ql \li390\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin390\itap0 
\rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext34 \slink35 Body Text Indent 2;}{\*\cs35 \additive \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f0\fs20 
\sbasedon10 \slink34 \slocked \ssemihidden Body Text Indent 2 Char;}{\s36\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af2\afs20\alang1025 \ltrch\fcs0 
\fs20\lang1033\langfe1033\loch\f2\hich\af2\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext36 \slink37 Plain Text;}{\*\cs37 \additive \rtlch\fcs1 \af2\afs20 \ltrch\fcs0 \f2\fs20 \sbasedon10 \slink36 \slocked \ssemihidden Plain Text Char;}}
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\qc \fi-720\li720\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1\afs32 
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\par }\pard \ltrpar\qc \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Revised 22-Sep-2008 for SIMH V3.8-1
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\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\loch\af1\hich\af1\dbch\af11\insrsid4550150 \hich\af1\dbch\af11\loch\f1 COPYRIGHT NOTICE
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \loch\af1\hich\af1\dbch\af11\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \loch\af1\hich\af1\dbch\af11\insrsid4550150 \hich\af1\dbch\af11\loch\f1 The following copyright notice applies to the SIMH source, binary, and documentation:
\par 
\par }\pard \ltrpar\s36\ql \li720\ri962\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin962\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \loch\af1\hich\af1\dbch\af11\insrsid4550150 \hich\af1\dbch\af11\loch\f1 
Original code published in 1993-2008, written by Robert M Supnik
\par \hich\af1\dbch\af11\loch\f1 Copyright (c) 1993-2008, Robert M Supnik
\par 
\par \hich\af1\dbch\af11\loch\f1 Permission is hereby granted, free of charge, to any person ob\hich\af1\dbch\af11\loch\f1 
taining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of t
\hich\af1\dbch\af11\loch\f1 h\hich\af1\dbch\af11\loch\f1 e Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
\par 
\par \hich\af1\dbch\af11\loch\f1 The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
\par 
\par \hich\af1\dbch\af11\loch\f1 THE SOFTWARE\hich\af1\dbch\af11\loch\f1 
 IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAG
\hich\af1\dbch\af11\loch\f1 E\hich\af1\dbch\af11\loch\f1 S OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\par \hich\af1\dbch\af11\loch\f1 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE  SOFTWARE.
\par 
\par \hich\af1\dbch\af11\loch\f1 Except as contained in this notice, the name of Robert M Supnik shall not be \hich\af1\dbch\af11\loch\f1 
used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik.
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08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300035003500000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.1}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Time Base\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048056 \\
h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300035003600000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.2}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Step Function\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048057 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310035003000340038003000350037000000fd}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.3}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048058 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300035003800000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 7}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.4}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Interrupt Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048059 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300035003900000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 7}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.5}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 I/O Dispatching\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048060 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300036003000000043}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 8}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.6}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048061 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300036003100000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 8}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Peripheral Device Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048062 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310035003000340038003000360032000000ff}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 9}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.1}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Timing\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048063 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300036003300000002}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 10}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.2}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Clock Calibration\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048064 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300036003400000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 11}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.3}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Idling\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048065 \\h }{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300036003500000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 12}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.4}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data I/O\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048066 \\h 
}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300036003600000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 12}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 
\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.}{\rtlch\fcs1 \ab0\ai0\af1 \ltrch\fcs0 
\b0\i0\f1\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Structures\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048067 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300036003700000059}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 14}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af1 \ltrch\fcs0 \b0\i0\f1\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_device Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048068 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300036003800000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 14}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.1}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Awidth and Aincr\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048069 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300036003900000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 15}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.2}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Flags\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048070 
\\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300037003000000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 15}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.3}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Context\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048071 \\h }
{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300037003100000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 16}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.4}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Examine and Deposit Routines\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048072 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300037003200000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 16}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.5}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Reset Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048073 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310035003000340038003000370033000000f9}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 16}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.6}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Boot Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048074 
\\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300037003400000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 16}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.7}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Attach and Detach Routines\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048075 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300037003500000001}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 16}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.8}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Size Change Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048076 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300037003600000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 17}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.9}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Debug Controls\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048077 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300037003700000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 17}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048078 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300037003800000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 18}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2.1}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Unit Flags\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048079 \\
h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310035003000340038003000370039000000bb}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 19}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2.2}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Service Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048080 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300038003000000076}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 19}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.3}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048081 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300038003100000001}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 19}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.3.1}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Register Flags\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048082 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300038003200000002}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 21}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048083 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300038003300000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 21}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4.1}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Validation Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048084 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f00630032003100350030003400380030003800340000002e}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 23}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4.2}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Display Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048085 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300038003500000059}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 23}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.5}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other Data Structures\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048086 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300038003600000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 24}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 
\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.}{\rtlch\fcs1 \ab0\ai0\af1 \ltrch\fcs0 
\b0\i0\f1\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Provided Routines\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048087 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300038003700000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 24}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af1 \ltrch\fcs0 \b0\i0\f1\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.1}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048088 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300038003800000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 24}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.2}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Binary Load and Dump\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048089 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300038003900000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 24}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.3}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Symbolic Examination and Deposit\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048090 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300039003000000001}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 24}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Optional Interfaces\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048091 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f00630032003100350030003400380030003900310000002d}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.1}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Once Only Initialization Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048092 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300039003200000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.2}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Address Input and Display\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc2150480\hich\af1\dbch\af31505\loch\f1 93 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300039003300000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 26}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.3}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Command Input and Post-Processing\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048094 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300039003400000001}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 26}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.4}{\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM-Specific Commands\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048095 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300039003500000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 26}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 

\par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 
\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.}{\rtlch\fcs1 \ab0\ai0\af1 \ltrch\fcs0 
\b0\i0\f1\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other SCP Facilities\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048096 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300039003600000002}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 27}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af1 \ltrch\fcs0 \b0\i0\f1\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 
\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.1}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Input/Output Formatting Library\tab }{\field\flddirty{\*\fldinst {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048097 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300039003700000005}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 27}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.2}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Multiplexer Emulation Library\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  PAGEREF _Toc215048098 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300039003800000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 28}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.3}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Magnetic Tape Emulation Library\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 PAGEREF _Toc215048099 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800300039003900000000}}}{\fldrslt {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 31}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 
\b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.4}{\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Breakpoint Support\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  PAGE
\hich\af1\dbch\af31505\loch\f1 REF _Toc215048100 \\h }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 {\*\datafield 
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f006300320031003500300034003800310030003000000000}}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 33}}}
\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af1\afs24 \ltrch\fcs0 \b0\f1\fs24\lang1024\langfe1024\noproof\insrsid4550150 
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 }}\pard\plain \ltrpar
\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj 
{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \page 
\par {\*\bkmkstart _Toc215048052}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af1\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Overview{\*\bkmkend _Toc215048052}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SIMH (history simulators) is a set of portable programs, written in C, which simulate various historically interesting \hich\af1\dbch\af31505\loch\f1 
computers.  This document describes how to design, write, and check out a new simulator for SIMH.  It is not an introduction to either the philosophy or external operation of SIMH, and the reader should be familiar with both of those topics before proceed
\hich\af1\dbch\af31505\loch\f1 i\hich\af1\dbch\af31505\loch\f1 
ng.  Nor is it a guide to the internal design or operation of SIMH, except insofar as those areas interact with simulator design.  Instead, this manual presents and explains the form, meaning, and operation of the interfaces between simulators and the SIM
\hich\af1\dbch\af31505\loch\f1 H\hich\af1\dbch\af31505\loch\f1  simulator control package.  It also offers some suggestions for utilizing the services SIMH offers and explains the constraints that all simulators operating within SIMH will experience.

\par 
\par \hich\af1\dbch\af31505\loch\f1 Some terminology: Each simulator consists of a standard }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 simulator c\hich\af1\dbch\af31505\loch\f1 ontrol package}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (SCP and related libraries), which provides a control framework and utility routines for a simulator; and a unique }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 virtual machine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (VM), which implements the simulated processor and selected peripherals.  A VM consists of multiple }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 devices}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , s\hich\af1\dbch\af31505\loch\f1 
uch as the CPU, paper tape reader, disk controller, etc.  Each controller consists of a named state space (called }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 registers}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ) and one or more }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 units}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  Each unit consists of a numbered state space (called a }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 data set}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ). }{\rtlch\fcs1 
\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
host computer}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is the system on which SIMH runs; the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 target computer}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is the system being simulated.
\par 
\par \hich\af1\dbch\af31505\loch\f1 SIMH is unabashedly based on the MIMIC simulation system, designed in the late 1960\hich\f1 \rquote \loch\f1 s by Len Fehskens, Mike McCarthy, and Bob Supnik.   This document is based on MIMIC\hich\f1 \rquote 
\hich\af1\dbch\af31505\loch\f1 \hich\f1 s published interface specification, \'93\loch\f1 \hich\f1 How to Write a Virtual Machine for the MIMIC Simulation System\'94\loch\f1 , by Len Fehskens and Bob Supnik.
\par 
\par {\*\bkmkstart _Toc215048053}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af1\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Types{\*\bkmkend _Toc215048053}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SIMH is written in C.  The host system must support (at least) 32-bit data type\hich\af1\dbch\af31505\loch\f1 
s (64-bit data types for the PDP-10 and other large-word target systems).  To cope with the vagaries of C data types, SIMH defines some unambiguous data types for its interfaces:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 SIMH data type\tab \tab \tab interpretation in typical 32-bit C
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 int8, uint8\tab \tab \tab signed \hich\af1\dbch\af31505\loch\f1 char, unsigned char
\par \tab \hich\af1\dbch\af31505\loch\f1 int16, uint16\tab \tab \tab signed short, unsigned short
\par \tab \hich\af1\dbch\af31505\loch\f1 int32, uint32\tab \tab \tab signed int, unsigned int
\par \tab \hich\af1\dbch\af31505\loch\f1 t_int64, t_uint64\tab \tab \tab long long, _int64 (system specific)
\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab \tab \tab simulated address, uint32 or t_uint64
\par \tab \hich\af1\dbch\af31505\loch\f1 t_value\tab \tab \tab \tab simulated value, uint32 or t_u\hich\af1\dbch\af31505\loch\f1 int64
\par \tab \hich\af1\dbch\af31505\loch\f1 t_svalue\tab \tab \tab simulated signed value, int32 or t_int64
\par \tab \hich\af1\dbch\af31505\loch\f1 t_mtrec\tab \tab \tab \tab mag tape record length, uint32
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab \tab \tab status code, int
\par \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab \tab \tab true/false value, int
\par 
\par \hich\af1\dbch\af31505\loch\f1 [The inconsistency in naming t_int64 and t_uint64 is due to Microsoft VC++, which uses int64\hich\af1\dbch\af31505\loch\f1  as a structure name member in the master Windows definitions file.]
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 In addition, SIMH defines structures for each of its major data elements:

\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEVICE}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 device definition structure
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 unit definition structure
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 register definition structure
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 modifier definition structure
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 command definition structure
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEBTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 debug table entry structure
\par 
\par {\*\bkmkstart _Toc215048054}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af1\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Organization{\*\bkmkend _Toc215048054}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 A virtual machine (VM) is a collection of devices bound together through their internal logic.  Each device is named and corresponds more or less to a hunk of hardware on the real machine; for example:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 VM device\tab \tab \tab Real machine hardware
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 CPU\tab \tab \tab \tab central p\hich\af1\dbch\af31505\loch\f1 rocessor and main memory
\par \tab \hich\af1\dbch\af31505\loch\f1 PTR\tab \tab \tab \tab paper tape reader controller and paper tape reader
\par \tab \hich\af1\dbch\af31505\loch\f1 TTI\tab \tab \tab \tab console keyboard
\par \tab \hich\af1\dbch\af31505\loch\f1 TTO\tab \tab \tab \tab console output
\par \tab \hich\af1\dbch\af31505\loch\f1 DKP\tab \tab \tab \tab disk pack controller and drives
\par 
\par \hich\af1\dbch\af31505\loch\f1 There may be more than one device per physical hardware entity, as for the console;\hich\af1\dbch\af31505\loch\f1 
 but for each user-accessible device there must be at least one.  One of these devices will have the pre-eminent responsibility for directing simulated operations.  Normally, this is the CPU, but it could be a higher-level entity, such as a bus master.

\par 
\par \hich\af1\dbch\af31505\loch\f1 Th\hich\af1\dbch\af31505\loch\f1 e VM actually runs as a subroutine of the simulator control package (SCP).  It provides a master routine for running simulated programs and other routines and data structures to implement SCP
\hich\f1 \rquote \loch\f1 s command and control functions.  The interfaces between a VM a\hich\af1\dbch\af31505\loch\f1 n\hich\af1\dbch\af31505\loch\f1 d SCP are relatively few:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 Interface\tab \tab \tab Function
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_name[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 simulator name string

\par \tab \hich\af1\dbch\af31505\loch\f1 REG *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_pc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 
pointer to simulated program counter
\par \tab \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 
maximum number of words in an instruction
\par \tab \hich\af1\dbch\af31505\loch\f1 DEVICE *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 
table of pointers to simulated d\hich\af1\dbch\af31505\loch\f1 evices, NULL terminated
\par \tab \hich\af1\dbch\af31505\loch\f1 char *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_messages[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 
table of pointers to error messages
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1  (\'85\loch\f1 )\tab \tab 
binary loader subroutine
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_inst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (void)\tab \tab 
instruction execution subroutine
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1  (\'85\loch\f1 )\tab \tab 
symbolic instruction parse subroutine
\par \tab \hich\af1\dbch\af31505\loch\f1 t_\hich\af1\dbch\af31505\loch\f1 stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
\hich\f1  (\'85\loch\f1 )\tab \tab symbolic instruction print subroutine
\par 
\par \hich\af1\dbch\af31505\loch\f1 In addition, there are six optional interfaces, which can be used for special situations, such as GUI implementations:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 Interface\tab \tab \tab \tab Function
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ) (void)\tab \tab 
\hich\af1\dbch\af31505\loch\f1 pointer to once-only initialization routine for VM
\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )
\tab pointer to address parsing routine
\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )
\tab pointer to address output routine
\par \tab \hich\af1\dbch\af31505\loch\f1 char (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 *sim_vm_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )\tab 
\tab pointer to command input routine
\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_\hich\af1\dbch\af31505\loch\f1 vm_post}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
\hich\f1 ) (\'85\loch\f1 )\tab \tab pointer to command post-processing routine
\par \tab \hich\af1\dbch\af31505\loch\f1 CTAB }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 *sim_vm_cmd}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 
pointer to simulator-specific command table
\par 
\par \hich\af1\dbch\af31505\loch\f1 There is no required organization for VM code.  The following convention has been used so far.  Let name be the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  of the real syste\hich\af1\dbch\af31505\loch\f1 m (i1401 for the IBM 1401; i1620 for the IBM 1620; pdp1 for the PDP-1; pdp18b for the other 18-bit PDP\hich\f1 \rquote \loch\f1 
s; pdp8 for the PDP-8; pdp11 for the PDP-11; nova for Nova; hp2100 for the HP 21XX; h316 for the Honeywell 315/516; gri for the GRI-909; pdp10 for the P\hich\af1\dbch\af31505\loch\f1 D\hich\af1\dbch\af31505\loch\f1 
P-10; vax for the VAX; sds for the SDS-940):
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .h contains definitions for the particular simulator
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 _sys.c contains all the SCP interfaces except the instruction simulator
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 _cpu.c contains the instruction simulator and CPU data structure\hich\af1\dbch\af31505\loch\f1 s
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 _stddev.c contains the peripherals which were standard with the real system.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 _lp.c contains the line printer.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 _mt.c contains the mag tape controller and drives, etc.
\par }\pard \ltrpar\ql \fi1440\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The SIMH standard definitions are in sim_defs.h.  The base compone
\hich\af1\dbch\af31505\loch\f1 nts of SIMH are:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 Source module\tab \tab header file\tab \tab module
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 scp.c\tab \tab \tab scp.h\tab \tab \tab control package
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_console.c\tab \tab sim_console.h\tab \tab terminal I/O library
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_fio.c\tab \tab sim_fio.h\tab \tab file I/O library
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_timer.c\tab \tab sim_timer.h\tab \tab timer library
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_sock.c\tab \tab sim_sock.h\tab \tab \hich\af1\dbch\af31505\loch\f1 socket I/O library
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_ether.c\tab \tab sim_ether.h\tab \tab Ethernet I/O library
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_tmxr.c\tab \tab sim_tmxr.h\tab \tab terminal multiplexer simulation library
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_tape.c\tab \tab sim_tape.h\tab \tab magtape simulation library
\par {\*\bkmkstart _Toc215048055}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 3.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CPU Organization{\*\bkmkend _Toc215048055}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Most CPU\hich\f1 \rquote \loch\f1 s perform at le\hich\af1\dbch\af31505\loch\f1 ast the following functions:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Time keeping
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction fetching
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Address decoding
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Execution of non-I/O instructions
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 I/O command processing
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Interrupt processing
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Instruction execution is actually the least complicated part of the design; memory and I/O organization should be tackled first.
\par {\*\bkmkstart _Toc215048056}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 3.1.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Time Base{\*\bkmkend _Toc215048056}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 In order to simulate asynchronous events, such as I/O completion, the VM must define\hich\af1\dbch\af31505\loch\f1 
 and keep a time base.  This can be accurate (for example, nanoseconds of execution) or arbitrary (for example, number of instructions executed), but it must be used consistently throughout the VM.  All existing VM\hich\f1 \rquote \loch\f1 
s count time in instructions.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The CPU is\hich\af1\dbch\af31505\loch\f1  responsible for counting down the event counter }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and calling the asynchronous event controller }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .  SCP does the record keeping for timing.
\par {\*\bkmkstart _Toc215048057}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 3.1.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Step Function{\*\bkmkend _Toc215048057}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP implements a stepping function using \hich\af1\dbch\af31505\loch\f1 
the step command.  STEP counts down a specified number of time units (as described in section 3.1.1) and then stops simulation.  The VM can override the STEP command\hich\f1 \rquote \loch\f1 s counts by calling routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_cancel_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls25\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat sim_cancel_step (void) \hich\f1 \endash \loch\f1  cancel STE\hich\af1\dbch\af31505\loch\f1 P count down.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The VM can then inspect variable }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 to see if a STEP command is in progress.  If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is non-zero, it represents the number of steps to execute.  The VM can count down }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  using its own counting method, such as cycles, instructions, or memory references.
\par {\*\bkmkstart _Toc215048058}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 3.1.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Organization{\*\bkmkend _Toc215048058}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The criterion for memory layout is very simple: use the SIMH data type that is as large as (or if necessary, larger tha\hich\af1\dbch\af31505\loch\f1 
n), the word length of the real machine.  Note that the criterion is word length, not addressability: the PDP-11 has byte addressable memory, but it is a 16-bit machine, and its memory is defined as uint16 M[].  It may seem tempting to define memory as a 
\hich\af1\dbch\af31505\loch\f1 u\hich\af1\dbch\af31505\loch\f1 
nion of int8 and int16 data types, but this would make the resulting VM endian-dependent.  Instead, the VM should be based on the underlying word size of the real machine, and byte manipulation should be done explicitly.  Examples:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 Simulator\tab \tab memory size\tab \tab \hich\af1\dbch\af31505\loch\f1 memory declaration
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 IBM 1620\tab \tab 5-bit\tab \tab \tab uint8
\par \tab \hich\af1\dbch\af31505\loch\f1 IBM 1401\tab \tab 7-bit\tab \tab \tab uint8
\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-8\tab \tab \tab 12-bit\tab \tab \tab uint16
\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-11, Nova\tab \tab 16-bit\tab \tab \tab uint16
\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-1\tab \tab \tab 18-bit\tab \tab \tab uint32
\par \tab \hich\af1\dbch\af31505\loch\f1 VAX\tab \tab \tab 32-bit\tab \tab \tab uint32
\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-10, IBM 7094\tab 36-bit\tab \tab \tab t_uint64
\par {\*\bkmkstart _Toc215048059}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 3.1.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Interrupt Organization{\*\bkmkend _Toc215048059}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The design of the VM\hich\f1 \rquote \loch\f1 s interrupt structure is a complex interaction between efficiency and fidelity to the hardware.  If the VM\hich\f1 \rquote \loch\f1 
s interrupt structure is too abstract, interrupt driven software may not run.  On the other hand, if it follows the \hich\af1\dbch\af31505\loch\f1 
hardware too literally, it may significantly reduce simulation speed.  One rule I can offer is to minimize the fetch-phase cost of interrupts, even if this complicates the (much less frequent) evaluation of the interrupt system following an I/O operation 
\hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 r asynchronous event.  Another is not to over-generalize; even if the real hardware could support 64 or 256 interrupting devices, the simulators will be running much smaller configurations.  I
\hich\f1 \rquote \loch\f1 ll start with a simple interrupt structure and then offer sugg\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 stions for generalization.
\par 
\par \hich\af1\dbch\af31505\loch\f1 
In the simplest structure, interrupt requests correspond to device flags and are kept in an interrupt request variable, with one flag per bit.  The fetch-phase evaluation of interrupts consists of two steps: are interrupts enabl
\hich\af1\dbch\af31505\loch\f1 ed, and is there an interrupt outstanding?  If all the interrupt requests are kept as single-bit flags in a variable, the fetch-phase test is very fast:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 if (int_enable && int_requests) \{\hich\f1  \'85\loch\f1 \hich\f1 process interrupt\'85\loch\f1  \}
\par 
\par \hich\af1\dbch\af31505\loch\f1 Indeed, the interrupt enable flag can be mad\hich\af1\dbch\af31505\loch\f1 e the highest bit in the interrupt request variable, and the two tests combined:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 if (int_requests > INT_ENABLE) \{\hich\f1  \'85\loch\f1 \hich\f1 process interrupt\'85\loch\f1  \}
\par 
\par \hich\af1\dbch\af31505\loch\f1 Setting or clearing device flags directly sets or clears the appropriate interrupt request flag:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 set: \tab \hich\af1\dbch\af31505\loch\f1 int_requests = int_requests | DEVICE_FLAG;
\par \tab \hich\af1\dbch\af31505\loch\f1 clear:\tab int_requests = int_requests & ~DEVICE_FLAG;
\par 
\par \hich\af1\dbch\af31505\loch\f1 At a slightly higher complexity, interrupt requests do not correspond directly to device flags but are based on masking the device flags with an enable (or disa\hich\af1\dbch\af31505\loch\f1 
ble) mask.  There are now two parallel variables: device flags and interrupt enable mask.  The fetch-phase test is now:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 If (int_enable && (dev_flags & int_enables)) \{\hich\f1  \'85\loch\f1 \hich\f1 process interrupt\'85\loch\f1  \}
\par 
\par \hich\af1\dbch\af31505\loch\f1 As a next step, the VM may keep a summary interrupt request vari\hich\af1\dbch\af31505\loch\f1 able, which is updated by any change to a device flag or interrupt enable/disable:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 enable:\tab int_requests = device_flags & int_enables;
\par \tab \hich\af1\dbch\af31505\loch\f1 disable:\tab int_requests = device_flags & ~int_disables;
\par 
\par \hich\af1\dbch\af31505\loch\f1 This simplifies the fetch phase test slightly.
\par 
\par \hich\af1\dbch\af31505\loch\f1 At yet higher co\hich\af1\dbch\af31505\loch\f1 
mplexity, the interrupt system may be too complex or too large to evaluate during the fetch-phase.  In this case, an interrupt pending flag is created, and it is evaluated by subroutine call whenever a change could occur (start of execution, I/O instructi
\hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 n issued, device time out occurs).  This makes fetch-phase evaluation simple and isolates interrupt evaluation to a common subroutine.
\par 
\par \hich\af1\dbch\af31505\loch\f1 If required for interrupt processing, the highest priority interrupting device can be determined by scanning the interru\hich\af1\dbch\af31505\loch\f1 
pt request variable from high priority to low until a set bit is found.  The bit position can then be back-mapped through a table to determine the address or interrupt vector of the interrupting device.
\par {\*\bkmkstart _Toc215048060}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 3.1.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 I/O Dispatching{\*\bkmkend _Toc215048060}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 I/O \hich\af1\dbch\af31505\loch\f1 dispatching consists of four steps:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Identify the I/O command and analyze for the device address.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Locate the selected device.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Break down the I/O command into standard fields.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Call the device processor.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Analyzing an I/O command is usually easy.\hich\af1\dbch\af31505\loch\f1 
  Most systems have one or more explicit I/O instructions containing an I/O command and a device address.  Memory mapped I/O is more complicated; the identification of a reference to I/O space becomes part of memory addressing.  This usually requires cent
\hich\af1\dbch\af31505\loch\f1 r\hich\af1\dbch\af31505\loch\f1 alizing memory reads and writes into subroutines, rather than as inline code.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Once an I/O command has been analyzed, the CPU must locate the device subroutine.  The simplest way is a large \hich\af1\dbch\af31505\loch\f1 
switch statement with hardwired subroutine calls. More modular is to call through a dispatch table, with NULL entries representing non-existent devices; this also simplifies support for modifiable device addresses and configurable devices.  Before calling
\hich\af1\dbch\af31505\loch\f1  \hich\af1\dbch\af31505\loch\f1 the device routine, the CPU usually breaks down the I/O command into standard fields.  This simplifies writing the peripheral simulator.
\par {\*\bkmkstart _Toc215048061}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 3.1.6\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution{\*\bkmkend _Toc215048061}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Instruction execution is the responsibility of VM subroutine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim\hich\af1\dbch\af31505\loch\f1 _instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  It is called from SCP as a result of a RUN, GO, CONT, or BOOT command.  It begins executing instructions at the current PC (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_PC}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to its register description block) and continues until halted by an error or an external event.
\par 
\par \hich\af1\dbch\af31505\loch\f1 When called,\hich\af1\dbch\af31505\loch\f1 
 the CPU needs to account for any state changes that the user made.  For example, it may need to re-evaluate whether an interrupt is pending, or restore frequently used state to local register variables for efficiency.  The actual instruction fetch and ex
\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 cute cycle is usually structured as a loop controlled by an error variable, e.g.,
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 reason = 0;
\par \tab \hich\af1\dbch\af31505\loch\f1 do \{\hich\f1  \'85\loch\f1  \} while (reason == 0);\tab or\tab while (reason == 0) \{\hich\f1  \'85\loch\f1  \}
\par 
\par \hich\af1\dbch\af31505\loch\f1 Within this loop, the usual order of events is:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If the event timer }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  has reached zer\hich\af1\dbch\af31505\loch\f1 o, process any timed events.  This is done by SCP subroutine }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  Because this is the polling mechanism for user-generated processor halts (^E), errors must be recognized immediately:
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li1440\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 if (sim_interval <= 0) \{
\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 if (reason = sim_process_event 
\hich\af1\dbch\af31505\loch\f1 ()) break;  \}
\par }\pard \ltrpar\ql \fi2160\li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Check for outstanding interrupts and process if required.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Check for other processor-unique events, such as wait-state outstanding or traps outstanding.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Check for an instruction breakpoint.  SCP has a comprehensive breakpoint facil\hich\af1\dbch\af31505\loch\f1 ity.  It allows a VM to define many different kinds of breakpoints.  The VM checks for execution (type E) breakpoints during instruction fetch.

\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Fetch the next instruction, increment the PC, optionally decode the address, and dispatch (via a switch stat\hich\af1\dbch\af31505\loch\f1 ement) for execution.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 A few guidelines for implementation:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls5\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls5\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
In general, code should reflect the hardware being simulated.  This is usually simplest and easiest to debug.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls5\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls5\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The VM should provide some debugging aids.  The existing CPU\hich\f1 
\rquote \hich\af1\dbch\af31505\loch\f1 s all provide multiple instruction breakpoints, a PC change queue, error stops on invalid instructions or operations, and symbolic examination and modification of memory.
\par {\*\bkmkstart _Toc215048062}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 3.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Peripheral Device Organization{\*\bkmkend _Toc215048062}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The basic elements of a\hich\af1\dbch\af31505\loch\f1 
 VM are devices, each corresponding roughly to a real chunk of hardware.  A device consists of register-based state and one or more units.  Thus, a multi-drive disk subsystem is a single device (representing the hardware of the real controller) and one or
\hich\af1\dbch\af31505\loch\f1  \hich\af1\dbch\af31505\loch\f1 
more units (each representing a single disk drive).  Sometimes the device and its unit are the same entity as, for example, in the case of a paper tape reader.  However, a single physical device, such as the console, may be broken up for convenience into 
\hich\af1\dbch\af31505\loch\f1 s\hich\af1\dbch\af31505\loch\f1 eparate input and output devices.
\par 
\par \hich\af1\dbch\af31505\loch\f1 In general, units correspond to individual sources of input or output (one tape transport, one A-to-D channel).  Units are the basic medium for both device timing and device I/O.  Except for the console, all I/O devices a
\hich\af1\dbch\af31505\loch\f1 re simulated as host-resident files.  SCP allows the user to make an explicit association between a host-resident file and a simulated hardware entity.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Both devices and units have state.  Devices operate on }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 registers}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 , which contain information about the s\hich\af1\dbch\af31505\loch\f1 tate of the device, and indirectly, about the state of the units.  Units operate on }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 data sets}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
, which may be thought of as individual instances of input or output, such as a disk pack or a punched paper tape.  In a typical multi-unit device, all units are t\hich\af1\dbch\af31505\loch\f1 
he same, and the device performs similar operations on all of them, depending on which one has been selected by the program being simulated.
\par 
\par \hich\af1\dbch\af31505\loch\f1 (Note: SIMH, like MIMIC, restricts registers to devices. Replicated registers, for example, disk drive current sta\hich\af1\dbch\af31505\loch\f1 te, are handled via register arrays.)
\par 
\par \hich\af1\dbch\af31505\loch\f1 For each structural level, SIMH defines, and the VM must supply, a corresponding data structure.  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_device}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structures correspond to devices, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  structures to registers, and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 structures to units.  These \hich\af1\dbch\af31505\loch\f1 structures are described in detail in section 4.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The primary functions of a peripheral are:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls6\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls6\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 command decoding and execution
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls6\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls6\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 device timing
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls6\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls6\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 data transmission.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Command decoding is fairly obvious.  At least one section of the peripheral code module \hich\af1\dbch\af31505\loch\f1 
will be devoted to processing directives issued by the CPU.  Typically, the command decoder will be responsible for register and flag manipulation, and for issuing or canceling I/O requests.  The former is easy, but the later requires a thorough understan
\hich\af1\dbch\af31505\loch\f1 d\hich\af1\dbch\af31505\loch\f1 ing of device timing.
\par {\*\bkmkstart _Toc215048063}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 3.2.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Timing{\*\bkmkend _Toc215048063}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The principal problem in I/O device simulation is imitating asynchronous operations in a sequential simulation environment.  Fortunately, the timing characteristics of most I/O devices do\hich\af1\dbch\af31505\loch\f1 
 not vary with external circumstances.  The distinction between devices whose timing is externally generated (e.g., console keyboard) and those whose timing is }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1049593 \hich\af1\dbch\af31505\loch\f1 internally}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  generated (disk, paper tape reader) is crucial.  With an externally timed device, the\hich\af1\dbch\af31505\loch\f1 
re is no way to know when an in-progress operation will begin or end; with an internally timed device, given the time when an operation starts, the end time can be calculated.
\par 
\par \hich\af1\dbch\af31505\loch\f1 For an internally timed device, the elapsed time between the start and conclusion of an operation is called the wait time.  Some typical internally timed devices and their wait times include:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 PTR (300 char/sec)\tab \tab 3.3 msec
\par \tab \hich\af1\dbch\af31505\loch\f1 PTP (50 char/sec)\tab \tab 20 msec
\par \tab \hich\af1\dbch\af31505\loch\f1 CLK \hich\af1\dbch\af31505\loch\f1 (line frequency)\tab \tab 16.6 msec
\par \tab \hich\af1\dbch\af31505\loch\f1 TTO (30 char/sec)\tab \tab 33 msec
\par 
\par \hich\af1\dbch\af31505\loch\f1 Mass storage devices, such as disks and tapes, do not have a fixed response time, but a start-to-finish time can be calculated based on current versus desired position, state of motion, etc.
\par 
\par \hich\af1\dbch\af31505\loch\f1 For an \hich\af1\dbch\af31505\loch\f1 externally timed device, there is no portable mechanism by which a VM can be notified of an external event (for example, a key stroke).  Accordingly, all current VM\hich\f1 \rquote 
\loch\f1 s poll for keyboard input, thus converting the externally timed keyboard to a pseudo-inter\hich\af1\dbch\af31505\loch\f1 n\hich\af1\dbch\af31505\loch\f1 
ally timed device.  A more general restriction is that SIMH is single-threaded.  Threaded operations must be done by polling using the unit timing mechanism, either with real units or fake units created expressly for polling.
\par 
\par \hich\af1\dbch\af31505\loch\f1 SCP provides the supporting r\hich\af1\dbch\af31505\loch\f1 
outines for device timing.  SCP maintains a list of devices (called active devices) that are in the process of timing out.  It also provides routines for querying or manipulating this list (called the active queue).  Lastly, it provides a routine for chec
\hich\af1\dbch\af31505\loch\f1 k\hich\af1\dbch\af31505\loch\f1 ing for timed-out units and executing a VM-specified action when a time-out occurs.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Device timing is done with the UNIT structure, described in section 4.  To set up a timed operation, the peripheral calculates a waiting period for a unit and places that \hich\af1\dbch\af31505\loch\f1 
unit on the active queue.  The CPU counts down the waiting period.  When the waiting period has expired, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  removes the unit from the active queue and calls a device subroutine.  A device may also cancel an outstanding timed operation and qu\hich\af1\dbch\af31505\loch\f1 
ery the state of the queue.  The timing subroutines are:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_activate}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, int32 wait).  This routine places the specified unit on the active queue with the specified waiting period.  A waiting period of 0 is legal; negative waits cause \hich\af1\dbch\af31505\loch\f1 
an error.  If the unit is already active, the active queue is not changed, and no error occurs.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_cancel}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr).  This routine removes the specified unit from the active queue.  If the unit is not on the queue, no error occurs.

\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32\hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_is_active}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr).  This routine tests whether a unit is in the active queue.  If it is, the routine returns the time (+1) remaining; if it is not, the routine returns 0.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 double }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_gtime}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (void).  This routine returns the time elapsed since t\hich\af1\dbch\af31505\loch\f1 he last RUN or BOOT command.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uint32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_grtime}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (void).  This routine returns the low-order 32b of the time elapsed since the last RUN or BOOT command.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_qcount}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (void).  This routine returns the number of entries on the clock queue.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (void).  This routine removes all timed out units from the active queue and calls the appropriate device subroutine to service the time-out.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  This variable counts down the first outstanding timed event.  If \hich\af1\dbch\af31505\loch\f1 \hich\f1 
there are no timed events outstanding, SCP counts down a \'93\loch\f1 \hich\f1 null interval\'94\loch\f1  of 10,000 time units.
\par {\*\bkmkstart _Toc215048064}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 3.2.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Clock Calibration{\*\bkmkend _Toc215048064}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The timing mechanism described in the previous section is approximate.  Devices, such as real-time clocks, whi\hich\af1\dbch\af31505\loch\f1 
ch track wall time will be inaccurate.  SCP provides routines to synchronize multiple simulated clocks (to a maximum of 8) to wall time.
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls15\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls15\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_rtcn_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 clock_interval, int32 clk).  This routine initializes the clock calibration mechanism fo\hich\af1\dbch\af31505\loch\f1 
r simulated clock }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 clk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The argument is returned as the result.
\par }\pard \ltrpar\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls15\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls15\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_rtcn_calb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 tickspersecond, int32 clk).  This routine calibrates simulated clock }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 clk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The argument is the number of clock ticks expected per second.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The VM must call }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_r\hich\af1\dbch\af31505\loch\f1 tcn_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  for each simulated clock in two places: in the prolog of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 , before instruction execution starts, and whenever the real-time clock is started.  The simulator calls }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_rtcn_calb}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to calculate the actual interval delay when the real-time clock is serviced:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 /* clock start */
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 if (!sim_is_active (&clk_unit)) sim_activate (&clk_unit, sim_rtcn_init (clk_delay, clkno));
\par \tab \hich\af1\dbch\af31505\loch\f1 etc.
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 /* clock service */
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 sim_activate (&clk_unit, sim_rtcb_\hich\af1\dbch\af31505\loch\f1 calb (clk_ticks_per_second, clkno);
\par 
\par \hich\af1\dbch\af31505\loch\f1 The real-time clock is usually simulated clock 0; other clocks are used for polling asynchronous multiplexers or intervals timers.
\par {\*\bkmkstart _Toc215048065}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 3.2.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Idling{\*\bkmkend _Toc215048065}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If a VM implements a free-running, calibrated cl\hich\af1\dbch\af31505\loch\f1 
ock of 100Hz or less, then the VM can also implement idling.  Idling is a way of pausing simulation when no real work is happening, without losing clock calibration.  The VM must detect when it is idle; it can then inform the host of this situation by cal
\hich\af1\dbch\af31505\loch\f1 l\hich\af1\dbch\af31505\loch\f1 ing }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls26\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (int32 clk, t_bool one_tick) \hich\f1 \endash \loch\f1  attempt to idle the VM until the next scheduled I/O event, using simulated clock }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 clk}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  as the time base, and decrement }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  by an appropriate number of cycles.  If a calibrated timer is not available, or the time until the next event is less than 1ms, decrement }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  by 1 if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 one_tick}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is TRUE; otherwise, leave sim_interval unchanged.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  returns TRUE if the VM actu\hich\af1\dbch\af31505\loch\f1 
ally idled, FALSE if it did not.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Because idling and throttling are mutually exclusive, the VM must inform SCP when idling is turned on or off:
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls26\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_set_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  informs SCP that idling is enabled.
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 _stat}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  sim_clr_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  informs SCP that idling is disabled.
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_show_idle}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  displays whether idling is enabled or disabled, as seen by SCP.
\par {\*\bkmkstart _Toc215048066}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 3.2.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data I/O{\*\bkmkend _Toc215048066}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 
For most devices, timing is half the battle (for clocks it is the entire war); the other half is I/O.  Some devices are simulated on real hardware (for example, Ethernet controllers).  Most I/O devices are simulated as files on t
\hich\af1\dbch\af31505\loch\f1 he host file system in little-endian format.  SCP provides facilities for associating files with units (ATTACH command) and for reading and writing data from and to devices in a endian- and size-independent way.
\par 
\par \hich\af1\dbch\af31505\loch\f1 For most devices, the VM designer does not \hich\af1\dbch\af31505\loch\f1 
have to be concerned about the formatting of simulated device files.  I/O occurs in 1, 2, 4, or 8 byte quantities; SCP automatically chooses the correct data size and corrects for byte ordering.  Specific issues:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Line printers should write data as 7-bi\hich\af1\dbch\af31505\loch\f1 
t ASCII, with newlines replacing carriage-return/line-feed sequences.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Disks should be viewed as linear data sets, from sector 0 of surface 0 of cylinder 0 to the last sector on the disk.  This allows easy transcription of real disks to files usable by \hich\af1\dbch\af31505\loch\f1 the simulator.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Magtapes, by convention, use a record based format.  Each record consists of a leading 32-bit record length, the record data (padded with a byte of 0 if the record length is odd), and a trailing 32-bit record length.  File marks are reco
\hich\af1\dbch\af31505\loch\f1 rded as one record length of 0.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Cards have 12 bits of data per column, but the data is most conveniently viewed as (ASCII) characters.  Column binary can be implemented using two successive characters per card column..
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Data I/O varies between fixed an\hich\af1\dbch\af31505\loch\f1 
d variable capacity devices, and between buffered and non-buffered devices.  A fixed capacity device differs from a variable capacity device in that the file attached to the former has a maximum size, while the file attached to the latter may expand indef
\hich\af1\dbch\af31505\loch\f1 i\hich\af1\dbch\af31505\loch\f1 
nitely.  A buffered device differs from a non-buffered device in that the former buffers its data set in host memory, while the latter maintains it as a file.  Most variable capacity devices (such as the paper tape reader and punch) are sequential; all bu
\hich\af1\dbch\af31505\loch\f1 f\hich\af1\dbch\af31505\loch\f1 fered devices are fixed capacity.
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 3.2.4.1\tab}}\pard \ltrpar\ql \fi-1080\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault\faauto\ls1\ilvl3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Reading and Writing Data
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The ATTACH command creates an association between a host file and an I/O unit.  For non-buffered devices, ATTACH stores the file pointer for the host file in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 fileref}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field of the UNIT structure.  For buffered devices, ATTACH reads the entire host file into a buffer pointed to by the }{\rtlch\fcs1 
\ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 filebuf }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
field of the UNIT structure.  If unit flag UNIT_MUSTBUF is set, the buffer is allocated dynamically; otherwise, it must be static\hich\af1\dbch\af31505\loch\f1 ally allocated.
\par 
\par \hich\af1\dbch\af31505\loch\f1 For non-buffered devices, I/O is done with standard C subroutines plus the SCP routines }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fread}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fwrite}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  }{\rtlch\fcs1 
\ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fread}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
sim_fwrite}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  are identical in calling sequence and function to fread and fwrite, respectively, but will correct \hich\af1\dbch\af31505\loch\f1 
for endian dependencies.  For buffered devices, I/O is done by copying data to or from the allocated buffer.  The device code must maintain the number (+1) of the highest address modified in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 hwmark}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field of the UNIT structure.  For both the non-buffere\hich\af1\dbch\af31505\loch\f1 
d and buffered cases, the device must perform all address calculations and positioning operations.
\par 
\par \hich\af1\dbch\af31505\loch\f1 SIMH provides capabilities to access files >2GB (the int32 position limit).  If a VM is compiled with flags USE_INT64 and USE_ADDR64 defined, then t_addr is\hich\af1\dbch\af31505\loch\f1 
 defined as t_uint64 rather than uint32.  Routine sim_fseek allows simulated devices to perform random access in large files:
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls24\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fseek}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *handle, t_addr position, int where)
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 sim_fseek is identical to standard C }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fseek}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
, with two exceptions: wher\hich\af1\dbch\af31505\loch\f1 e = SEEK_END is not supported, and the position argument can be 64b wide.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The DETACH command breaks the association between a host file and an I/O unit.  For buffered devices, DETACH writes the allocated buffer back to the host file.
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 3.2.4.2\tab}}\pard \ltrpar\ql \fi-1080\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault\faauto\ls1\ilvl3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Console I/O
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 SCP provides three routines for console I/O.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_poll_char }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
(void).  This routine polls for keyboard input.  If there is a character, it returns SCPE_KFLAG + the character.  If the user typed the interrupt character (^E), it returns SCPE_STOP.  \hich\af1\dbch\af31505\loch\f1 
If the console is attached to a Telnet connection, and the connection is lost, the routine returns SCPE_LOST.  If there is no input, it returns SCPE_OK.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_putchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 cha\hich\af1\dbch\af31505\loch\f1 
r).  This routine types the specified ASCII character to the console.  If the console is attached to a Telnet connection, and the connection is lost, the routine returns SCPE_LOST.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0
\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_putchar_s}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 char).  This routine outputs the specified \hich\af1\dbch\af31505\loch\f1 
ASCII character to the console.  If the console is attached to a Telnet connection, and the connection is lost, the routine returns SCPE_LOST; if the connection is backlogged, the routine returns SCPE_STALL.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\*\bkmkstart _Toc215048067}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af1\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Structures{\*\bkmkend _Toc215048067}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 T\hich\af1\dbch\af31505\loch\f1 
he devices, units, and registers that make up a VM are formally described through a set of data structures which interface the VM to the control portions of SCP.  The devices themselves are pointed to by the device list array }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Within a devic\hich\af1\dbch\af31505\loch\f1 
e, both units and registers are allocated contiguously as arrays of structures.  In addition, many devices allow the user to set or clear options via a modifications table.
\par 
\par \hich\af1\dbch\af31505\loch\f1 \hich\f1 Note that a device must always have at least one unit, even if that unit is not needed for simulation purposes.  A device must always point to a valid register table, but the register table can consist of just the 
\'93\loch\f1 \hich\f1 end of table\'94\loch\f1  entry.
\par {\*\bkmkstart _Toc215048068}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 4.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim\hich\af1\dbch\af31505\loch\f1 _device Structure{\*\bkmkend _Toc215048068}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Devices are defined by the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_device}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure (typedef 
}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEVICE}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_device \{
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *name;\tab \tab \tab \tab /* name */
\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_unit \tab *units;\tab \tab \tab \tab /* units */
\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_reg\tab *registers;\tab \tab \tab /* registers */
\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_mtab\tab *modi\hich\af1\dbch\af31505\loch\f1 fiers;\tab \tab \tab /* modifiers */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab numunits;\tab \tab \tab /* #units */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab aradix;\tab \tab \tab \tab /* address radix */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab awidth;\tab \tab \tab \tab /* address width */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab aincr;\tab \tab \tab \tab /* addr increment */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dradix;\tab \tab \tab \tab /* data radix */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dwidth;\tab \tab \tab \tab /* data width */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_s\hich\af1\dbch\af31505\loch\f1 tat\tab \tab (*examine)();\tab \tab \tab /* examine routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*deposit)();\tab \tab \tab /* deposit routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*reset)();\tab \tab \tab /* reset routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*boot)();\tab \tab \tab /* boot routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*attach)();\tab \tab \tab /* attach routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*detach)();\tab \tab \tab /* detach rou\hich\af1\dbch\af31505\loch\f1 tine */
\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *ctxt}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 * context */

\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dctrl;\tab \tab \tab \tab /* debug control flags */
\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_debtab debflags;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
* debug flag names */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*msize)();\tab \tab \tab /* memory size change */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *lname;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 logical name */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 device name, string of all capital alphanumeric characters.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 units}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structures, or NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 registers}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structures, or NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 modifiers}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to array\hich\af1\dbch\af31505\loch\f1  of }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structures, or NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 numunits}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  \tab number of units in this device.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aradix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 radix for input and display of device addresses, 2 to 16 inclusive.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of a device address, 1 to 64 inclusive.
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab 
\hich\af1\dbch\af31505\loch\f1 increment between device add\hich\af1\dbch\af31505\loch\f1 resses, normally 1; however, byte addressed devices with 16-bit words specify 2, with 32-bit words 4.
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dradix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 radix for input and display of device data, 2 to 16 inclusive.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dwidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of device data, 1 to 64 inclusive.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 examine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of special\hich\af1\dbch\af31505\loch\f1 
 device data read routine, or NULL if none is required.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 deposit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 
address of special device data write routine, or NULL if none is required.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of device reset routine, or NULL if none is required.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 boot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of device bootstrap routine, or N\hich\af1\dbch\af31505\loch\f1 
ULL if none is required.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of special device attach routine, or NULL if none is required.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of special device detach routine, or NULL if none is required.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ctxt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of VM-specific device context table, or NULL if none is req
\hich\af1\dbch\af31505\loch\f1 uired.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 device flags.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debug control flags.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pointer to array of sim_debtab structures, or NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 msize}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of memory size change routine, or NULL if none is required.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lname\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pointer to logical name string.
\par {\*\bkmkstart _Toc215048069}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.1.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Awidth and Aincr{\*\bkmkend _Toc215048069}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 
\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  field specifies the width of the VM\hich\f1 \rquote \loch\f1 \hich\f1 s fundamental computer \'93\loch\f1 \hich\f1 word\'94\loch\f1 .  For example, on the PDP-11, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is 16b, even though memory is byte-addressable.  The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field specifies how many addressing units comp\hich\af1\dbch\af31505\loch\f1 \hich\f1 rise the fundamental \'93\loch\f1 \hich\f1 word\'94
\loch\f1 .  For example, on the PDP-11, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is 2 (2 bytes per word).
\par 
\par \hich\af1\dbch\af31505\loch\f1 If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is greater than 1, SCP assumes that data is naturally aligned on addresses that are multiples of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 .  VM\hich\f1 \rquote \hich\af1\dbch\af31505\loch\f1 s that support arbitrary byte alignment of data (like the VAX) can follow one of two strategies:
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls24\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  = 8 and }{
\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  = 1 and support only byte access in the examine/deposit routines.
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 to the fundamental sizes and support unali\hich\af1\dbch\af31505\loch\f1 gned data access in the examine/deposit routines.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 In a byte-addressable VM, SAVE and RESTORE will require (memory_size_bytes / }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ) iterations to save or restore memory.  Thus, it is significantly more efficient to use word-wide rather than byte-wide me\hich\af1\dbch\af31505\loch\f1 
mory; but requirements for unaligned access can add significantly to the complexity of the examine and deposit routines.
\par {\*\bkmkstart _Toc215048070}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.1.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Flags{\*\bkmkend _Toc215048070}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
field contains indicators of current device status.  SIMH defines 2 flags:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fla\hich\af1\dbch\af31505\loch\f1 g name\tab \tab meaning if set
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISABLE\tab \tab device can be set enabled or disabled
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DIS\tab \tab device is currently disabled
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DYNM\tab \tab device requires call on }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 msize}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 routine to change memory size
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_NET\tab \tab device attaches to the network rather than a file
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DEBUG\tab \tab \hich\af1\dbch\af31505\loch\f1 device supports SET DEBUG command
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_RAW\tab \tab device supports raw I/O
\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_RAWONLY\tab device supports only raw I/O
\par 
\par \hich\af1\dbch\af31505\loch\f1 Starting at bit position DEV_V_UF, the remaining flags are device-specific.  Device flags are automatically saved and restored; the device need\hich\af1\dbch\af31505\loch\f1  not supply a register for these bits.
\par {\*\bkmkstart _Toc215048071}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.1.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Context{\*\bkmkend _Toc215048071}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The field contains a pointer to a VM-specific device context table, if required.  SIMH never accesses this field.  The context field allows VM-specific code to walk VM-specific\hich\af1\dbch\af31505\loch\f1 
 data structures from the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 root pointer.
\par {\*\bkmkstart _Toc215048072}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.1.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Examine and Deposit Routines{\*\bkmkend _Toc215048072}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 
For devices which maintain their data sets as host files, SCP implements the examine and deposit data functions.  However, devices which maintain their data sets as private state (for example, the CPU) must supply special examine and deposit routines.  Th
\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1  calling sequences are:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 examine_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (t_val *eval_array, t_addr addr, UNIT *uptr, int32 switches) \hich\f1 \endash \loch\f1  Copy }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  consecutive addresses for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , starting at }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , into }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 eval_array}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The }{\rtlch\fcs1 
\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  variable has bit<n> set if the n\hich\f1 \rquote \loch\f1 th letter was 
\hich\af1\dbch\af31505\loch\f1 specified as a switch to the examine command.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 deposit_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (t_val value, t_addr addr, UNIT *uptr, int32 switches) \hich\f1 \endash \loch\f1  Store the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  in the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  for unit }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  variable is the same as for the examine routine.
\par {\*\bkmkstart _Toc215048073}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.1.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Reset Routine{\*\bkmkend _Toc215048073}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The reset routine implements the device reset function for the RESET, RUN, and BOOT commands.  Its calling sequence is:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reset_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (DEVICE *dptr) \hich\f1 
\endash \loch\f1  Reset the specified device to its initial state.
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 A ty\hich\af1\dbch\af31505\loch\f1 
pical reset routine clears all device flags and cancels any outstanding timing operations.  Switch \hich\f1 \endash \loch\f1 p specifies a reset to power-up state.
\par {\*\bkmkstart _Toc215048074}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.1.6\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Boot Routine{\*\bkmkend _Toc215048074}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If a device responds to a BOOT command, the boot routine implements the\hich\af1\dbch\af31505\loch\f1  bootstrapping function.  Its calling sequence is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 boot_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 unit_num, DEVICE *dptr) \hich\f1 \endash \loch\f1  Bootstrap unit  }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 unit_num}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  on the device }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 A typical bootstrap routine copies a bootstrap loader into main memory and sets the PC to the starting ad\hich\af1\dbch\af31505\loch\f1 dress of the loader.  SCP then starts simulation at the specified address.
\par {\*\bkmkstart _Toc215048075}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.1.7\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Attach and Detach Routines{\*\bkmkend _Toc215048075}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Normally, the ATTACH and DETACH commands are handled by SCP.  However, devices which need to pre- or post-process these c\hich\af1\dbch\af31505\loch\f1 
ommands must supply special attach and detach routines.  The calling sequences are:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 attach_routine }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, char *file) \hich\f1 \endash \loch\f1  Attach the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 file}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to the unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 .
\par \hich\af1\dbch\af31505\loch\f1 Sim_switches contains the command switch; bit SIM_SW_REST indicates that attac\hich\af1\dbch\af31505\loch\f1 h is being called by the RESTORE command rather than the ATTACH command.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Detach unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 In practice, these routines usually invoke the standard SCP routines, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 attach_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
, respectively.  For example, here are special attach and detach routines to update line printer error state:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 t_stat lpt_attach (UNIT *uptr, char *cptr) \{
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 t_stat r;
\par \hich\af2\dbch\af31505\loch\f2 if ((r = attach_unit (uptr, cptr)) != SCPE_OK) return r;
\par \hich\af2\dbch\af31505\loch\f2 lpt_error = 0;
\par \hich\af2\dbch\af31505\loch\f2 return SCPE_OK;
\par \}
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 
\par \hich\af2\dbch\af31505\loch\f2 t_stat lpt_detach (UNIT *uptr) \{
\par \tab \hich\af2\dbch\af31505\loch\f2 lpt_error = 1;
\par \tab \hich\af2\dbch\af31505\loch\f2 return detach_unit (uptr);
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \}
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 
If the VM specifies an ATTACH or DETACH routine, SCP bypasses its normal tests before calling the VM routine.  Thus, a VM DETACH routine cannot be assured that the unit is actually attached and must test the unit flags if required.
\par 
\par \hich\af1\dbch\af31505\loch\f1 SCP executes a DETACH A\hich\af1\dbch\af31505\loch\f1 LL command as part of simulator exit.  Normally, DETACH ALL only calls a unit\hich\f1 \rquote \loch\f1 s detach routine if the unit\hich\f1 \rquote \loch\f1 
s UNIT_ATT flag is set.  During simulator exit, the detach routine is also called if the unit is not flagged as attachable (UNIT_ATTABLE is not set).\hich\af1\dbch\af31505\loch\f1 
  This allows the detach routine of a non-attachable unit to function as a simulator-specific cleanup routine for the unit, device, or entire simulator.
\par {\*\bkmkstart _Toc215048076}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.1.8\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Size Change Routine{\*\bkmkend _Toc215048076}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Most units instantiate any memory array at \hich\af1\dbch\af31505\loch\f1 the maximum size possible.  This allows apparent memory size to be changed by varying the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 field in the unit structure.  For some devices (like the VAX CPU), instantiating the maximum memory size would impose a significant resource burden if less memo\hich\af1\dbch\af31505\loch\f1 
ry was actually needed.  These devices must provide a routine, the memory size change routine, for RESTORE to use if memory size must be changed:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 change_mem_size}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  Change the capacity (memory size) of
\hich\af1\dbch\af31505\loch\f1  unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 arguments are included for compatibility with the SET command\hich\f1 \rquote \loch\f1 s validation routine calling sequence.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par {\*\bkmkstart _Toc215048077}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.1.9\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Debug Controls{\*\bkmkend _Toc215048077}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Devices can support debug printouts.  Debug printouts are controlled by the SET \{NO\}DEBUG command, which specifies where debug output should be printed; and by the SET <device> \{NO\}
DEBUG command, which enables or disables individual debug printouts.
\par 
\par \hich\af1\dbch\af31505\loch\f1 If a \hich\af1\dbch\af31505\loch\f1 device supports debug printouts, device flag DEV_DEBUG must be set.  Field }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is used for the debug control flags.  If a device supports only a single debug on/off flag, then the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field should be set to NULL.  If a device supports multiple debug\hich\af1\dbch\af31505\loch\f1  on/off flags, then the correspondence between bit positions in }{
\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and debug flag names is specified by table  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to a continguous array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_debtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  structures (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEBTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
).  Each sim_debtab structure specifies a single deb\hich\af1\dbch\af31505\loch\f1 ug flag:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 Struct sim_debtab \{
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab name}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab \tab /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
* flag name */
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab mask;\tab \tab \tab \tab /* control bit */
\par \tab \tab \}\hich\af1\dbch\af31505\loch\f1 ;
\par 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 name\tab \tab name of the debug flag.
\par \tab \hich\af1\dbch\af31505\loch\f1 mask\tab \tab bit mask of the debug flag.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The array is terminated with a NULL entry.
\par {\*\bkmkstart _Toc215048078}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 4.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit Structure{\*\bkmkend _Toc215048078}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Units are allocated as contiguous array.  Each unit is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_unit \{
\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_unit\tab *next;\tab \tab \tab \tab /* next active */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*action)();\tab \tab \tab /* action routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *filename;\tab \tab \tab /* open file name */
\par \tab \hich\af1\dbch\af31505\loch\f1 FILE\tab \tab *fileref;\tab \tab \tab \tab /* file reference */
\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *filebuf;\tab \tab \tab \tab /* memory buffer */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab hwmark;\tab \tab \tab /* high water mark */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab time;\tab \tab \tab \tab /* time out */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab capac;\tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* capacity */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab pos;\tab \tab \tab \tab /* file position */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab buf;\tab \tab \tab \tab /* buffer */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab wait;\tab \tab \tab \tab /* wait */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u3;\tab \tab \tab \tab /* device specific */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u4;\tab \tab \tab \tab /* device specific */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u5;\tab \tab \tab \tab /* device specific */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u6;\tab \tab \tab \tab /* device specific */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 next}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 pointer to next unit in active queue, NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 action}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of unit time-out service routine.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 filename}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to name of attached file, NULL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fileref}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to FILE structure of attached file, NU
\hich\af1\dbch\af31505\loch\f1 LL if none.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 hwmark}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 buffered devices only; highest modified address, + 1.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 time}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 increment until time-out beyond previous unit in active queue.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 unit flags.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 unit capacity, 0 if variable.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pos}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 sequential devices only; next device address to be re
\hich\af1\dbch\af31505\loch\f1 ad or written.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 by convention, the unit buffer, but can be used for other purposes.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 wait}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 by convention, the unit wait time, but can be used for other purposes.

\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u3}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 user-defined.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u4}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 user-defined.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u5\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 user-defined.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u6\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 user-defined.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 buf, wait, u3, u4, u5, u6, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and parts of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  are all saved and restored by the SAVE and RESTORE commands and thus can be used for unit state which must be preserved.
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 UDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is available to fill in the common fields of a UNIT.  It is invoked by
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \tab \hich\af1\dbch\af31505\loch\f1 UDA\hich\af1\dbch\af31505\loch\f1 TA\tab \tab (action_routine, flags, capacity)
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Fields after }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  can be filled in manually, e.g,
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 UNIT lpt_unit = 
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2  UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE, 0), 500 \};
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 defines the line printer as a sequential unit with a wait time of 500.
\par {\*\bkmkstart _Toc215048079}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.2.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Unit \hich\af1\dbch\af31505\loch\f1 Flags{\*\bkmkend _Toc215048079}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
field contains indicators of current unit status.  SIMH defines 12 flags:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag name\tab \tab meaning if set
\par 
\par \hich\af1\dbch\af31505\loch\f1 UNIT_ATTABLE\tab the unit responds to ATTACH and DETACH.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_RO\tab \tab the unit is currently read only.
\par \hich\af1\dbch\af31505\loch\f1 UNIX_FIX\tab \tab \hich\af1\dbch\af31505\loch\f1 the unit is fixed capacity.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_SEQ\tab \tab the unit is sequential.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_ATT\tab \tab the unit is currently attached to a file.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_BINK\tab \tab \hich\f1 the unit measures \'93\loch\f1 \hich\f1 K\'94\loch\f1  as 1024, rather than 1000.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_BUFABLE\tab the unit buffers its data set in memory.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_MUSTBUF\tab \hich\af1\dbch\af31505\loch\f1 the unit allocates its data buffer dynamically.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_BUF\tab \tab the unit is currently buffering its data set in memory.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_ROABLE\tab \tab the unit can be ATTACHed read only.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_DISABLE\tab \tab the unit responds to ENABLE and DISABLE.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_DIS\tab \tab the unit is currently disabl\hich\af1\dbch\af31505\loch\f1 ed.
\par \hich\af1\dbch\af31505\loch\f1 UNIT_RAW\tab \tab the unit is attached in RAW mode.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Starting at bit position UNIT_V_UF, the remaining flags are unit-specific.  Unit-specific flags are set and cleared with the SET and CLEAR commands, which reference the MTAB array (see below).  Unit-specific
\hich\af1\dbch\af31505\loch\f1  flags and UNIT_DIS are automatically saved and restored; the device need not supply a register for these bits.
\par {\*\bkmkstart _Toc215048080}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.2.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Service Routine{\*\bkmkend _Toc215048080}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 This routine is called by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 when a unit times out.  Its calling sequence is:
\par 
\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 _stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 service_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr)
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The status returned by the service routine is passed by }{\rtlch\fcs1 
\ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  back to the CPU.
\par {\*\bkmkstart _Toc215048081}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 4.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg Structure{\*\bkmkend _Toc215048081}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Registers are allocated as contiguous array, with a NULL register at the end.  E\hich\af1\dbch\af31505\loch\f1 ach register is defined with a }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct reg \{
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *name;\tab \tab \tab \tab /* name */
\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *loc;\tab \tab \tab \tab /* location */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab radix;\tab \tab \tab \tab /* radix */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab width;\tab \tab \tab \tab /* width */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab offset;\tab \tab \tab \tab /* starting bit */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab depth;\tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* save depth */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab qptr;\tab \tab \tab \tab /* current queue pointer */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 device name, string of all capital alphanumeric characters.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 loc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to location of the register value.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 radix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 radix for input and display of data, 2 to 16 inclusive.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 width}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of data, 1 to 32 inclusive.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 width\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 bit offset (from right end of data).
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 depth\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 size of data array (normally 1).
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 flags and formatting information.
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 qptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 for a circular queue\hich\af1\dbch\af31505\loch\f1 
, the entry number for the first entry
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 depth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1  field is used with \'93\loch\f1 
\hich\f1 arrayed registers\'94\loch\f1 .  Arrayed registers are used to represent structures with multiple data values, such as the locations in a transfer buffer; or structures which are replicated in every\hich\af1\dbch\af31505\loch\f1 
 unit, such as a drive status register.  The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 qptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1  field is used with \'93
\loch\f1 \hich\f1 queued registers\'94\loch\f1 .  Queued registers are arrays that are organized as circular queues, such as the PC change queue.
\par 
\par \hich\af1\dbch\af31505\loch\f1 A register that is 32b or less keeps its data in a 32b scalar variabl\hich\af1\dbch\af31505\loch\f1 
e (signed or unsigned).  A register that is 33b or more keeps its data in a 64b scalar variable (signed or unsigned).  There are several exceptions to this rule:
\par 
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls27\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 An arrayed register keeps its data in a C-array whose SIMH data type is as large as (or if \hich\af1\dbch\af31505\loch\f1 
necessary, larger than), the width of a register element.  For example, an array of 6b registers would keep its data in a uint8 (or int8) array; an array of 16b registers would keep its data in a uint16 (or int16) array; an array of 24b registers would ke
\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 p its data in a uint32 (or int32) array.
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af3\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 
A register flagged with REG_FIT obeys the sizing rules of an arrayed register, rather than a normal scalar register.  This is useful for aliasing registers into memory or into structures.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Macros }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ORDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DRDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , a\hich\af1\dbch\af31505\loch\f1 nd }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 HRDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  define right-justified octal, decimal, and hexidecimal registers, respectively.  They are invoked by:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 xRDATA\tab (name, location, width)
\par 
\par \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 FLDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 defines a one-bit binary flag at an arbitrary offset in a 32-bit word.  It is invoked by:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 FLDATA\tab (name, location, bit_position)
\par 
\par \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 GRDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 defines a register with arbitrary location and radix.  It is invoked by:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 GRDATA\tab (name, location, radix, width, bit_position)
\par 
\par \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 BRDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 defines an arrayed register whose data is kept in a standard C \hich\af1\dbch\af31505\loch\f1 array.  It is invoked by:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 BRDATA\tab (name, location, radix, width, depth)
\par 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 For all of these macros, the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field can be filled in manually, e.g.,
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 REG lpt_reg = \{
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \tab \{\hich\af2\dbch\af31505\loch\f2  DRDATA\tab (POS, lpt_unit.pos, 31), PV_LFT \}\hich\f2 , \'85\loch\f2  \}

\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Finally, macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 URDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  defines an arrayed
\hich\af1\dbch\af31505\loch\f1  register whose data is part of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 structure.  This macro must be used with great care.  If the fields are set up wrong, or the data is actually kept somewhere else, storing through this register declaration can trample over memory.  The macro is inv\hich\af1\dbch\af31505\loch\f1 oked by:

\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 URDATA\tab (name, location, radix, width, offset, depth, flags)
\par 
\par \hich\af1\dbch\af31505\loch\f1 The location should be an offset in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
structure for unit 0.  The width should be 32 for an int32 or uint32 field, and T_ADDR_W for a t_addr filed.  The flags can be any of the n\hich\af1\dbch\af31505\loch\f1 ormal register flags; REG_UNIT will be OR\hich\f1 \rquote \loch\f1 
d in automatically.  For example, the following declares an arrayed register of all the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 position fields in a device with 4 units:
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \{\hich\af2\dbch\af31505\loch\f2  URDATA\tab (POS, dev_unit[0].pos, 8, T_ADDR_W, 0, 4, 0) \}
\par {\*\bkmkstart _Toc215048082}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.3.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Re\hich\af1\dbch\af31505\loch\f1 gister Flags{\*\bkmkend _Toc215048082}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field contains indicators that control register examination and deposit.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag name\tab \tab meaning if specified
\par 
\par \hich\af1\dbch\af31505\loch\f1 PV_RZRO\tab \tab print register right justified with leading zeroes.
\par \hich\af1\dbch\af31505\loch\f1 PV_RSPC\tab \tab \hich\af1\dbch\af31505\loch\f1 print register right justified with leading spaces.
\par \hich\af1\dbch\af31505\loch\f1 PV_LEFT\tab \tab print register left justified.
\par \hich\af1\dbch\af31505\loch\f1 REG_RO\tab \tab register is read only.
\par \hich\af1\dbch\af31505\loch\f1 REG_HIDDEN\tab \tab register is hidden (will not appear in EXAMINE STATE).
\par \hich\af1\dbch\af31505\loch\f1 REG_HRO\tab \tab register is read only and hidden.
\par \hich\af1\dbch\af31505\loch\f1 REG_NZ\tab \tab new register va\hich\af1\dbch\af31505\loch\f1 lues must be non-zero.
\par \hich\af1\dbch\af31505\loch\f1 REG_UNIT\tab \tab register resides in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure.

\par \hich\af1\dbch\af31505\loch\f1 REG_CIRC\tab \tab register is a circular queue.
\par \hich\af1\dbch\af31505\loch\f1 REG_VMIO\tab \tab register is displayed and parsed using VM data routines.
\par \hich\af1\dbch\af31505\loch\f1 REG_VMAD\tab \tab register is displayed and parsed using VM address routines.
\par \hich\af1\dbch\af31505\loch\f1 REG_FI\hich\af1\dbch\af31505\loch\f1 T\tab \tab register container uses arrayed rather than scalar size rules.
\par {\*\bkmkstart _Toc215048083}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 4.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab Structure{\*\bkmkend _Toc215048083}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device-specific SHOW and SET commands are processed using the modifications array, which is allocated as contiguous array, with a NULL at th\hich\af1\dbch\af31505\loch\f1 
e end.  Each possible modification is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure (synonym }{
\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ), which has the following fields:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_mtab \{
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab mask;\tab \tab \tab \tab /* mask */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab match;\tab \tab \tab \tab /* match */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *pstring;\tab \tab \tab /* print string */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *mstring;\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* match string */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*valid)();\tab \tab \tab /* validation routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*disp)();\tab \tab \tab /* display routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *desc}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab \tab /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
* location descriptor */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 MTAB supports two different structure interpretations: regular and extended.  A regular MTAB entry modifies flags in the UNIT flags word; the descriptor entry is not used.  The fields are the following:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 bit mask for testing the unit.}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab 
\hich\af1\dbch\af31505\loch\f1 value to be stored (SET) or compared (SHOW)
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string printed on a match (SHOW), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string to be matched (SET), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 valid}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of validation routine (SET), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 disp\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 address of dis\hich\af1\dbch\af31505\loch\f1 play routine (SHOW), or NULL

\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 For SET, a regular MTAB entry is interpreted as follows:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  entry exists.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the SET parameter matches the }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Call the validation routine, if any.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Apply the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  value\hich\af1\dbch\af31505\loch\f1  to the UNIT flags word and then or in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  value. 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 For SHOW, a regular MTAB entry is interpreted as follows:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  entry exists.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the UNIT flags word, masked with the }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  value, equals the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  value.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If a display routine exists, call it, otherwise
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Print the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Extended MTAB entries have a different interpretation:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 entry flags
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB_XTD\tab extended entry
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VDV\tab valid for devices
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VUN\tab valid for units
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VAL\tab takes a value
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_NMO\tab valid only in named SHOW
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_NC\tab do not convert option value to upper case
\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_SHP\tab SHOW parameter takes optional value
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab 
\hich\af1\dbch\af31505\loch\f1 value to be stored (SET)
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string printed on a match (SHOW), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to c\hich\af1\dbch\af31505\loch\f1 
haracter string to be matched (SET), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 valid}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of validation routine (SET), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 disp\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 address of display routine (SHOW), or NULL
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pointer to a REG structure (MTAB_VAL set) or
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 a validation-specific structure (MTAB_VAL clear)
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 For SET, an\hich\af1\dbch\af31505\loch\f1  extended MTAB entry is interpreted as follows:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  entry exists.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the SET parameter matches the }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Test to see if the entry is valid for the type of SET being done (SET device or SET unit).
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If a \hich\af1\dbch\af31505\loch\f1 
validation routine exists, call it and return its status.  The validation routine is responsible for storing the result. 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is NULL, exit.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 6.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 If MTAB_VAL is set, parse the SET option for \'93\loch\f1 \hich\f1 
option=n\'94\loch\f1 , and store the value n in the register describe\hich\af1\dbch\af31505\loch\f1 d by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 7.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Otherwise, store the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  value in the int32 pointed to by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 For SHOW, an extended MTAB entry is interpreted as follows:
\par 
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  entry exists.
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
Test to see if the entry is valid for the type of SHOW being done (device or unit).
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If a display routine exists, call it, otherwise,
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 If MTAB_VAL is set, print \'93\loch\f1 \hich\f1 pstring=n\'94
\loch\f1 , where the value, radix, and width are taken from the register described by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 d\hich\af1\dbch\af31505\loch\f1 esc}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , otherwise,
\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f1\fs20 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0
\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Print the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SHOW [dev|unit] <modifier>\{=<value>\} is a special case.  Only two kinds of modifiers can be displayed individually: an extended MTAB entry that takes a value; and any MTAB entry with both a display routine and a }{
\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstr\hich\af1\dbch\af31505\loch\f1 ing}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  Recall that if a display routine exists, SHOW does not use the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 entry.  For displaying a named modifier, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is used as the string match.  This allows implementation of complex display routines that are only invoked by name, e.g.,
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 MTAB c\hich\af2\dbch\af31505\loch\f2 pu_tab[] = \{
\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  mask, value, \'93\loch\f2 \hich\f2 normal\'94\loch\f2 \hich\f2 , \'93\loch\f2 \hich\f2 NORMAL\'94\loch\f2 , NULL, NULL, NULL \},
\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, \'93\loch\f2 \hich\f2 SPECIAL\'94,
\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 NULL, NULL, NULL, &spec_disp \},
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \tab \{\hich\af2\dbch\af31505\loch\f2  0 \}
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \}\hich\af2\dbch\af31505\loch\f2 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 A SHOW CPU command will display only the modifier named NORMAL; but SHOW CPU SPECIAL will invoke\hich\af1\dbch\af31505\loch\f1  the special display routine.
\par {\*\bkmkstart _Toc215048084}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.4.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Validation Routine{\*\bkmkend _Toc215048084}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The validation routine can be used to validate input during SET processing.  It can make other state changes required by the modification or initiate additional dialogs neede\hich\af1\dbch\af31505\loch\f1 
d by the modifier.  Its calling sequence is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 validation_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, int32 value, char *cptr, void *desc) \hich\f1 \endash \loch\f1  test that }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  can be set to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to the value portion of the parameter string (any characters after the = sign\hich\af1\dbch\af31505\loch\f1 
); if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is NULL, no value was given.  }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  or int32 used to store the parameter.
\par {\*\bkmkstart _Toc215048085}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 4.4.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Display Routine{\*\bkmkend _Toc215048085}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The display routine is called during SHOW processing to display device- or unit-specific state.  Its call\hich\af1\dbch\af31505\loch\f1 ing sequence is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 display_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *st, UNIT *uptr, int value, void *desc) \hich\f1 \endash \loch\f1  output device- or unit-specific state for }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  If the modifier is regular MTAB entry, or an extended entry without MTAB_SHP set, }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to the stru\hich\af1\dbch\af31505\loch\f1 cture in the MTAB entry.  If the modifier is an extended MTAB entry with MTAB_SHP set, }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to the optional value string or is NULL if no value was supplied.  }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is the value field of the matched MTAB entry.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 When the display routine is called for a regular MTAB entry, SHOW has output the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  argument but has not appended a newline.  When it is called for an extended MTAB entry, SHOW hasn\hich\f1 \rquote \loch\f1 t output anything.  SHOW will append a newline after the display rout\hich\af1\dbch\af31505\loch\f1 
ine returns, except for entries with the MTAB_NMO flag set.
\par {\*\bkmkstart _Toc215048086}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 4.5\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other Data Structures{\*\bkmkend _Toc215048086}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_name[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is a character array containing the VM name.
\par 
\par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 contains the maximum number of words needed to hold the largest instruction or data item in the VM.  Examine and deposit will process up to }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  words.
\par 
\par \hich\af1\dbch\af31505\loch\f1 DEVICE *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is an array of pointers to all the devices in the VM.  It is terminated by a\hich\af1\dbch\af31505\loch\f1  NULL.  By convention, the CPU is always the first device in the array.
\par 
\par \hich\af1\dbch\af31505\loch\f1 REG *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_PC}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to the }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure for the program counter.  By convention, the PC is always the first register in the CPU\hich\f1 
\rquote \loch\f1 s register array.
\par 
\par \hich\af1\dbch\af31505\loch\f1 char *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_messages[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is an arra
\hich\af1\dbch\af31505\loch\f1 y of pointers to character strings, corresponding to error status returns greater than zero.  If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  returns status code n > 0, then }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_message[n]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  is printed by SCP.
\par 
\par {\*\bkmkstart _Toc215048087}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af1\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Provided Routines{\*\bkmkend _Toc215048087}
\par {\*\bkmkstart _Toc215048088}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 5.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instructio\hich\af1\dbch\af31505\loch\f1 n Execution{\*\bkmkend _Toc215048088}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Instruction execution is performed by routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  Its calling sequence is:
\par 
\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (void) \hich\f1 \endash \loch\f1  execute from current PC until error or halt.
\par {\*\bkmkstart _Toc215048089}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 5.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Binary Load and Dump{\*\bkmkend _Toc215048089}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If the VM responds to t\hich\af1\dbch\af31505\loch\f1 he LOAD (or DUMP) command, the load routine (dump routine) is implemented by routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Its calling sequence is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *fptr, char *buf, char *fnam, t_bool flag) - If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  = 0, load data from binary file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fptr}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 = 1, dump da\hich\af1\dbch\af31505\loch\f1 ta to binary file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  For either command, }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  contains any VM-specific arguments, and }{\rtlch\fcs1 
\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fnam}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  contains the file name.  
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If LOAD or DUMP is not implemented, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 should simply return SCPE_ARG.  The LOAD and DUMP commands open and close the specified fi\hich\af1\dbch\af31505\loch\f1 le for }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 .
\par {\*\bkmkstart _Toc215048090}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 5.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Symbolic Examination and Deposit{\*\bkmkend _Toc215048090}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If the VM provides symbolic examination and deposit of data, it must provide two routines, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  for output and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 for input.  Their calling sequences are:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 switch) \hich\f1 \endash \loch\f1  Based on the }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  variable, symbolically output to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ofile}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  the data in array }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  at the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 in unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (char *cptr, t_addr addr, U
\hich\af1\dbch\af31505\loch\f1 NIT *uptr, t_value *val, int32 switch) \hich\f1 \endash \loch\f1  Based on the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  variable, parse character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 for a symbolic value }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  at the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  in unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If symbolic processing is not implemented, or the output value or input string cannot be parsed\hich\af1\dbch\af31505\loch\f1 
, these routines should return SCPE_ARG.  If the processing was successful and consumed more than a single word, then these routines should return extra number of addressing units consumed as a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 negative}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  number.  If the processing was successful and consume\hich\af1\dbch\af31505\loch\f1 
d a single addressing unit, then these routines should return SCPE_OK.  For example, PDP-11 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  would respond as follows to various inputs:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 input\tab \tab \tab \tab return value
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 XYZGH\tab \tab \tab \tab SCPE_ARG
\par \tab \hich\af1\dbch\af31505\loch\f1 MOV R0,R1\tab \tab \tab -1
\par \tab \hich\af1\dbch\af31505\loch\f1 MOV #4,R5\tab \tab \tab -3
\par \tab \hich\af1\dbch\af31505\loch\f1 MOV 1234,5670\tab \tab -5
\par 
\par \hich\af1\dbch\af31505\loch\f1 There is an im\hich\af1\dbch\af31505\loch\f1 plicit relationship between the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  arguments and the device\hich\f1 \rquote 
\loch\f1 s }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  fields.  Each entry in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is assumed to represent }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  addressing units, starting at }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 :
\par 
\par \ltrrow}\trowd \irow0\irowband0\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
\trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[0]\cell \hich\af1\dbch\af31505\loch\f1 addr + 0\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow0\irowband0\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
\trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 
{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[1]\cell \hich\af1\dbch\af31505\loch\f1 addr + aincr\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1
\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow1\irowband1\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 
\trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr
\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow
}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[2]\cell \hich\af1\dbch\af31505\loch\f1 addr + (2 * aincr)\cell }\pard \ltrpar
\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow2\irowband2\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl
\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 
\clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil 
\cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[3]\cell \hich\af1\dbch\af31505\loch\f1 addr + (3 * aincr)\cell 
}\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow3\irowband3\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 
\trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 
\cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :\cell 
\hich\af1\dbch\af31505\loch\f1 :\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow4\irowband4\lastrow \ltrrow
\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr
\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Because }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is typically filled in and stored by calls on the device\hich\f1 \rquote \loch\f1 s examine and deposit routines, respectively, the examine and deposit routines and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  fparse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  must agree on the expected width of items in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , an
\hich\af1\dbch\af31505\loch\f1 d on the alignment of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Further, if }{\rtlch\fcs1 
\ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fparse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  wants to modify a storage unit narrower than }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , it must insert the new data into the appropriate entry in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  without destroying surrounding fields.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The interpretation of switch values is arbitrary,\hich\af1\dbch\af31505\loch\f1  but the following are used by existing VM\hich\f1 \rquote \loch\f1 s:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 switch\tab \tab \tab \tab interpretation
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 -a\tab \tab \tab \tab single character
\par \tab \hich\af1\dbch\af31505\loch\f1 -c\tab \tab \tab \tab character string
\par \tab \hich\af1\dbch\af31505\loch\f1 -m\tab \tab \tab \tab instruction mnemonic
\par 
\par \hich\af1\dbch\af31505\loch\f1 In addition, on input, a leading \hich\f1 \lquote \loch\f1  (apostrophe) is interpreted to mean a single character, and a leading \loch\af1\dbch\af31505\hich\f1 \'93\loch\f1 
 (double quote) is interpreted to mean a character string.
\par {\*\bkmkstart _Toc215048091}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 5.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Optional Interfaces{\*\bkmkend _Toc215048091}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 For greater flexibility, SCP provides some optional interfaces that can be used to extend its command input, command processing, and command post\hich\af1\dbch\af31505\loch\f1 
-processing capabilities.  These interfaces are strictly optional and are off by default.  Using them requires intimate knowledge of how SCP functions internally and is not recommended to the novice VM writer.
\par {\*\bkmkstart _Toc215048092}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 5.4.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Once Only Initialization Ro\hich\af1\dbch\af31505\loch\f1 utine{\*\bkmkend _Toc215048092}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 
)(void).  This is a \'93\loch\f1 \hich\f1 weak global\'94\loch\f1 ; if no other module defines this value, it will default to NULL.  A VM requiring special initialization should fill in this pointer with the address of its special ini
\hich\af1\dbch\af31505\loch\f1 tialization routine:
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 void sim_special_init (void);
\par \tab \hich\af2\dbch\af31505\loch\f2 void (*sim_vm_init)(void) = &sim_special_init;
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The special initialization routine can perform any actions required by the VM.  If the other optional interfaces are to be used, the initialization routin\hich\af1\dbch\af31505\loch\f1 
e can fill in the appropriate pointers; however, this can just as easily be done in the CPU reset routine.
\par {\*\bkmkstart _Toc215048093}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 5.4.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Address Input and Display{\*\bkmkend _Toc215048093}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer t_addr *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
)(DEVICE *, char *, char **).  This is ini\hich\af1\dbch\af31505\loch\f1 
tialized to NULL.  If it is filled in by the VM, SCP will use the specified routine to parse addresses in place of its standard numerical input routine.  The calling sequence for the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  routine is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_addr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (DEVICE *dptr, ch\hich\af1\dbch\af31505\loch\f1 ar *cptr, char **optr) \hich\f1 \endash \loch\f1 
 parse the string pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  as an address for the device pointed to by }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  o}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  points to the first character not successfully parsed.  If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  == }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 optr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , parsing failed.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer void *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 )(F
\hich\af1\dbch\af31505\loch\f1 ILE *, DEVICE *, t_addr).  This is initialized to NULL.  If it is filled in by the VM, SCP will use the specified routine to print addresses in place of its standard numerical output routine.  The calling sequence for the }{
\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  routine is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_\hich\af1\dbch\af31505\loch\f1 addr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *stream, DEVICE *dptr, t_addr addr) \hich\f1 \endash \loch\f1  output address }{\rtlch\fcs1 
\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 stream}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  in the format required by the device pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 .
\par {\*\bkmkstart _Toc215048094}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 5.4.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Command Input and Post-Processing{\*\bkmkend _Toc215048094}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer char* (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_v\hich\af1\dbch\af31505\loch\f1 m_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 )(char *, int32 *, FILE *).  This is initialized to NULL.  If it is filled in by the VM, SCP will use the specified routine to obtain command input in place of its standard routine, read_line.  The calling sequence for the }
{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  routine is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ch\hich\af1\dbch\af31505\loch\f1 ar }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 
\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_input}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (char *buf, int32 *max, FILE *stream) \hich\f1 \endash \loch\f1  read the next command line from }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 stream}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and store it in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , up to a maximum of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  characters
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The routine is expected to strip off leading whitespace characters and to return NULL on end of file.
\par 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer void *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_post}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
)(t_bool from_scp).  This is initialized to NULL.  If filled in by the VM, SCP will call the specified routine at the end of every command.  This allows the VM to update any local state, such as a GUI console display\hich\af1\dbch\af31505\loch\f1 
.  The calling sequence for the vm_post routine is:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_vm_postupdate}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (t_bool from_scp) \hich\f1 \endash \loch\f1  if called from SCP, the argument }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 from_scp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is TRUE; otherwise, it is FALSE.
\par {\*\bkmkstart _Toc215048095}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af1 \ltrch\fcs0 \f1 \hich\af1\dbch\af31505\loch\f1 5.4.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM-Specific Commands{\*\bkmkend _Toc215048095}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer CTAB *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_cmd}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  This is initialized to NULL.  If filled in by the VM, SCP interprets it as a pointer to SCP command table.  This command table is checked before user input is looked up in the standard command table.
\par 
\par \hich\af1\dbch\af31505\loch\f1 A command table is allocated as a contiguo\hich\af1\dbch\af31505\loch\f1 us array.  Each entry is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_ctab}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_ctab \{
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *name;\tab \tab \tab \tab /* name */
\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*action)();\tab \tab \tab /* action routine */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab arg;\tab \tab \tab \tab /* argument */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *help;\tab \tab \tab \tab /* help string */
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If the first word o\hich\af1\dbch\af31505\loch\f1 f a command line matches ctab.name, then the action routine is called with the following arguments:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 action_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 arg, char *buf) \hich\f1 \endash \loch\f1  process input string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  based on optional argument }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 arg}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The string passed to the action routine starts at t\hich\af1\dbch\af31505\loch\f1 he first non-blank character past the command name.
\par {\*\bkmkstart _Toc215048096}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af1\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28 \hich\af1\dbch\af31505\loch\f1 6.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other SCP Facilities{\*\bkmkend _Toc215048096}
\par {\*\bkmkstart _Toc215048097}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 6.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Input/Output Formatting Library{\*\bkmkend _Toc215048097}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SIMH provides routines to convert ASCII input characters to the format expected VM, and to convert VM-supplied ASCII characters to C-standard format.  The routines are
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_tt_inpcvt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 c, uint32 mode) \hich\f1 \endash \loch\f1  convert input character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 c}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  according to the\hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mode }{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 specification and return the converted result (-1 if the character is not valid in the specified mode).
\par 
\par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_outcvt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 c, uint32 mode) \hich\f1 
\endash \loch\f1  convert output character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 c}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  according to the }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  specification and return the converted result (-1 i\hich\af1\dbch\af31505\loch\f1 
f the character is not valid in the specified mode).
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The supported modes are:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_8B\tab 8b mode; no conversion
\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_7B\tab 7b mode; the high-order bit is masked off
\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_7P\tab 7b printable mode; the high-order bit is masked off
\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 In addition, \hich\af1\dbch\af31505\loch\f1 on output, if the character is not printable,
\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 -1 is returned
\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_UC\tab 7b upper case mode; the high-order bit is masked off
\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 In addition, lower case is converted to upper case
\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 If the character is not printable, -1 is returned
\par 
\par \hich\af1\dbch\af31505\loch\f1 On input, TTUF\hich\af1\dbch\af31505\loch\f1 _MODE_UC has an additional modifier, TTUF_MODE_KSR, which forces the high order bit to be set rather than cleared.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The set of printable control characters is contained in the global bit-vector variable }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Each bit represents the character corr\hich\af1\dbch\af31505\loch\f1 
esponding to the bit number (e.g., bit 0 represents NUL, bit 1 represents SOH, etc.).  If a bit is set, the corresponding control character is considered printable.  It initially contains the following characters: BEL, BS, HT, LF, and CR.  The set may be 
\hich\af1\dbch\af31505\loch\f1 m\hich\af1\dbch\af31505\loch\f1 anipulated with these routines:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_set_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (int32 flag, char *cptr) \hich\f1 \endash \loch\f1  set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to the value pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ; return SCPE_2FARG if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  is null or points to a null string, or SCPE_ARG if the value cannot be converted or does not contai\hich\af1\dbch\af31505\loch\f1 n at least CR and LF.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_show_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) \hich\f1 \endash \loch\f1  output the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  value to the stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Note that the DEL character is always considered non-printable and will be suppressed in the UC and\hich\af1\dbch\af31505\loch\f1  7P modes.
\par 
\par {\*\bkmkstart _Toc215048098}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 6.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Multiplexer Emulation Library{\*\bkmkend _Toc215048098}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SIMH supports the use of multiple terminals.  All terminals except the cons\hich\af1\dbch\af31505\loch\f1 
ole are accessed via Telnet.  SIMH provides two supporting libraries for implementing multiple terminals: sim_tmxr.c (and its header file, sim_tmxr.h), which provide OS-independent support routines for terminal multiplexers; and sim_sock.c (and its header
\hich\af1\dbch\af31505\loch\f1  \hich\af1\dbch\af31505\loch\f1 file, sim_sock.h), which provide OS-dependent socket routines.  Sim_sock.c is implemented under Windows, VMS, UNIX, and MacOS.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Two basic data structures define the multiple terminals.  Individual lines are defined by an array of  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmln}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structures (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TMLN}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct tmln \{
\par \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab conn;\tab \tab \tab \tab /* line conn */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab ipad;\tab \tab \tab \tab /* IP address */
\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab cnms;\tab \tab \tab \tab /* connect  time ms */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab tsta;\tab \tab \tab \tab /* Telnet state */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rcve;\tab \tab \tab \tab /* rcv enable */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab xmte;\tab \tab \tab \tab /* xmt enable */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab dstb;\tab \tab \tab \tab /* d\hich\af1\dbch\af31505\loch\f1 isable Tlnt bin */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxbpr;\tab \tab \tab \tab /* rcv buf remove */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxbpi;\tab \tab \tab \tab /* rcv buf insert */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxcnt;\tab \tab \tab \tab /* rcv count */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbpr;\tab \tab \tab \tab /* xmt buf remove */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbpi;\tab \tab \tab \tab /* xmt buf insert */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txcnt;\tab \tab \tab \tab /* xmt count */
\par \tab \hich\af1\dbch\af31505\loch\f1 FILE\tab \tab *txlog\hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab \tab /* xmt log file */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *txlogname;\tab \tab \tab /* xmt log file name */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab rxb[TMXR_MAXBUF];\tab \tab /* rcv buffer */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab rbr[TMXR_MAXBUF];\tab \tab /* rcv break */
\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab txb[TMXR_MAXBUF];\tab \tab /* xmt buffer */
\par \tab \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 conn}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 connection socket (0 = disconnected)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tsta}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 Telnet state
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rcve}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive enable flag (0 = disabled)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 xmte}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit flow control flag (0 = transmit disabled)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dstb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 Telnet bin mode disabled
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxbp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 r\tab \tab receive buffer remove pointer
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxbpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive buffer insert\hich\af1\dbch\af31505\loch\f1  pointer
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxcnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive count
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txbpr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer remove pointer
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txbpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer insert pointer
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txcnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit count
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txlog}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to log file descriptor
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txlogname}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to log file name
\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab 
\hich\af1\dbch\af31505\loch\f1 receive buffer
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rbr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive buffer break fla\hich\af1\dbch\af31505\loch\f1 gs
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txb}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer
\par 
\par \hich\af1\dbch\af31505\loch\f1 The overall set of extra terminals is defined by the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TMXR}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ):
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct tmxr \{
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab lines;\tab \tab \tab \tab /* # lines */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab port;\tab \tab \tab \tab /* listening port */
\par \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab master;\tab \tab \tab \tab /* master socket */
\par \tab \hich\af1\dbch\af31505\loch\f1 TMLN\tab \tab *ldsc;\tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* pointer to line descriptors */
\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab *lnorder;\tab \tab \tab /* line connection order */
\par \tab \hich\af1\dbch\af31505\loch\f1 DEVICE\tab *dptr;\tab \tab \tab \tab /* multiplexer device */
\par \tab \}\hich\af1\dbch\af31505\loch\f1 ;
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The fields are the following:
\par 
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 number of lines (constant)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 port}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 master listening port (specified by ATTACH command)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 master listening socket (filled in by ATTACH command)
\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ldsc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 array of line descriptors
\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab 
\hich\af1\dbch\af31505\loch\f1 array of line numbers in order of connection sequence, or NULL if user-defined connection order is not required
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to the multiplexer\hich\f1 \rquote \loch\f1 s DEVICE 
\hich\af1\dbch\af31505\loch\f1 structure, or NULL if the device is to be derived from the UNIT passed to the first attach call.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 The number of elements in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ldsc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and }{\rtlch\fcs1 
\ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  arrays must equal the value of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field.  Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to NULL if the connection order feature is not nee\hich\af1\dbch\af31505\loch\f1 ded.  If the first element of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  array is \hich\f1 \endash \loch\f1 1, then the default ascending sequential connection order is used.  Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to NULL if the device should be derived from the unit passed to the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  call.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Library sim_tmxr.c provides the followin\hich\af1\dbch\af31505\loch\f1 g routines to support Telnet-based terminals:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 tmxr_poll_conn}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp) \hich\f1 \endash \loch\f1  poll for a new connection to the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  If there is a new connection, the routine resets all the line descriptor state (including receive enable) and retu
\hich\af1\dbch\af31505\loch\f1 rns the line number (index to line descriptor) for the new connection.  If there isn\hich\f1 \rquote \loch\f1 t a new connection, the routine returns \hich\f1 \endash \loch\f1 1.
\par 
\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_reset_ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp) \hich\f1 \endash \loch\f1 
 reset the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  The connection is closed and all line descriptor state is res\hich\af1\dbch\af31505\loch\f1 et.
\par 
\par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_getc_ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp) \hich\f1 \endash \loch\f1 
 return the next available character from the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  If a character is available, the return variable is:
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 (1 << TMXR_V_VALID) | character
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If no character is available, the return variable is 0.
\par 
\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 mxr_poll_rx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (TMXR *mp) \hich\f1 \endash \loch\f1  poll for input available on the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 . 
\par 
\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_rqln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp) \hich\f1 \endash \loch\f1 
 return the number of characters in the receive queue of the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_putc_ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (TMLN *lp, int32 chr) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1  output character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 chr }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
to the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  Possible errors are SCPE_LOST (connection lost) and SCPE_STALL (connection backlogged).
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_poll_tx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp) 
\hich\f1 \endash \loch\f1  poll for output complete on the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 .
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_tqln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp\hich\af1\dbch\af31505\loch\f1 ) 
\hich\f1 \endash \loch\f1  return the number of characters in the transmit queue of the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp, UNIT *uptr, char *cptr) 
\hich\f1 \endash \loch\f1  attach the port contained in character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 to the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_\hich\af1\dbch\af31505\loch\f1 open_master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (TMXR *mp, char *cptr) \hich\f1 \endash \loch\f1  associate the port contained in character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  to the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  This routine is a subset of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (TMXR *mp, UNIT *uptr) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1  detach all connections for the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  and unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_close_master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMXR *mp) \hich\f1 \endash \loch\f1 
 close the master port for the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  This routine is a subset of}{
\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  tmxr_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 .
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_ex}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (t_value *vptr, t_addr addr, 
\hich\af1\dbch\af31505\loch\f1 UNIT *uptr, int32 sw) \hich\f1 \endash \loch\f1  stub examine routine, needed because the extra terminals are marked as attached; always returns an error.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_dep}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (t_value val, t_addr addr, UNIT *uptr, int32 sw) \hich\f1 \endash \loch\f1  stub deposit routine, needed because the extra terminals a\hich\af1\dbch\af31505\loch\f1 re marked as detached; always returns an error.
\par }\pard \ltrpar\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \fi360\li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 tmxr_linemsg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (TMLN *lp, char *msg) \hich\f1 \endash \loch\f1  output character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to line }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 .
\par 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_fconns}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, TMLN *lp, int32 ln) \hich\f1 \endash \loch\f1  output connection status to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  for the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  If }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is >= 0, preface the output with the specified line number.
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_fstats}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *st, TMLN *lp, int32 ln) \hich\f1 
\endash \loch\f1  output connection statistics to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  for the line described by }{
\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is >= 0, preface the output with the specified line number.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_st\hich\af1\dbch\af31505\loch\f1 at }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_dscln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, int32 val, char *cptr, void *mp) \hich\f1 \endash \loch\f1  parse the string pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  for a decimal line number.  If the line number is valid, disconnect the specified line in the terminal multiplexer described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The calling sequence allo\hich\af1\dbch\af31505\loch\f1 ws }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_dscln}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to be used as an MTAB processing routine.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_set_lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  set the line connection order array associated with the TMXR structure pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The string pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  is parsed for a semicolon-delimited list of ranges.  Ranges are of the form:
\par 
\par }\pard \ltrpar\ql \fi-2160\li3600\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin3600\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1-line2\tab ascending sequence from }{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 
\b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2  to }{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line2}{\rtlch\fcs1 \af2 
\ltrch\fcs0 \f2\insrsid4550150 
\par \hich\af2\dbch\af31505\loch\f2 line1/length\tab ascending sequence from }{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2  to }{
\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 +}{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 
\hich\af2\dbch\af31505\loch\f2 length}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 -1
\par \hich\af2\dbch\af31505\loch\f2 ALL\tab ascending sequence of all lines defined by the multiplexer
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 T\hich\af1\dbch\af31505\loch\f1 he line order array must provide an int32 element for each line.  The calling sequence allows }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
tmxr_set_lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to be used as an MTAB processing routine.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  output the line connection or\hich\af1\dbch\af31505\loch\f1 der associated multiplexer (TMXR *) }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid4550150 \hich\af0\dbch\af31505\loch\f0  }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  The order is rendered as a semicolon-delimited list of ranges.  The calling sequence allows }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to be used as an MTAB processing routine.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (FILE *st, UNI
\hich\af1\dbch\af31505\loch\f1 T *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  outputs the summary status of the multiplexer (TMXR *) }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_cstat}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  outputs either the connections (val = 1) or the statistics (val = 0) of the \hich\af1\dbch\af31505\loch\f1 multiplexer (TMXR *) }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Also checks for multiplexer not attached, or all lines disconnected.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  outputs the number of lines in the terminal multiplexer (TMXR *) I to strea\hich\af1\dbch\af31505\loch\f1 m I.
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
The OS-dependent socket routines should not need to be accessed by the terminal simulators. 
\par {\*\bkmkstart _Toc215048099}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 6.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Magnetic Tape Emulation Library{\*\bkmkend _Toc215048099}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SIMH supports the use of emulated magnetic tapes.  Magnetic tapes are emulated as disk files c\hich\af1\dbch\af31505\loch\f1 \hich\f1 
ontaining both data records and metadata markers; the format is fully described in the paper \'93\loch\f1 \hich\f1 SIMH Magtape Representation and Handling\'94\loch\f1 
.  SIMH provides a supporting library, sim_tape.c (and its header file, sim_tape.h), that abstracts handling of magnetic\hich\af1\dbch\af31505\loch\f1  \hich\af1\dbch\af31505\loch\f1 
tapes.  This allows support for multiple tape formats, without change to magnetic device simulators.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The magtape library does not require any special data structures.  However, it does define some additional unit flags:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 MTUF_WLK\tab \tab unit is write locked
\par 
\par \hich\af1\dbch\af31505\loch\f1 If magtape simulators need to define private unit flags, those flags should begin at bit number MTUF_V_UF instead of UNIT_V_UF.  The magtape library maintains the current magtape position in the }{\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pos}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  field of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  structure.
\par 
\par \hich\af1\dbch\af31505\loch\f1 Library sim_tape.c provides\hich\af1\dbch\af31505\loch\f1  the following routines to support emulated magnetic tapes:
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_tape_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, char *cptr) \hich\f1 \endash \loch\f1  Attach tape unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 uptr }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Tape 
\par \hich\af1\dbch\af31505\loch\f1 Simulators should call this routine, rather than the standard attach_unit routine, to allow for future\hich\af1\dbch\af31505\loch\f1  expansion of format support.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Detach tape unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  from its current file.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_set_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  Set the tape format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  to the format specified by string\hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  Write the tape format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1  Set the tape capacity \hich\af1\dbch\af31505\loch\f1 for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  to the capacity, in MB, specified by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1  Write the capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_rdrecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, uint8 
\hich\af1\dbch\af31505\loch\f1 *buf, t_mtrlnt *tbc, t_mtrlnt max) \hich\f1 \endash \loch\f1  Forward read the next record on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  of size }{\rtlch\fcs1 \ai\af1 
\ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Return the actual record size in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 .
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_rdrecr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, uint8 *buf, t_mtrlnt *tbc, t_mtrlnt max) \hich\f1 \endash \loch\f1  Reverse read the next record \hich\af1\dbch\af31505\loch\f1 on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 
\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 of size }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Return the actual record size in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  Note that the record is returned in forward order, that is, byte 0 of the record is stored in buf[0], and so on.

\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrrecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, uint8 buf, t_mtrlnt tbc)\hich\af1\dbch\af31505\loch\f1  \hich\f1 \endash \loch\f1  Write buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  of size }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  as the next record on unit }{\rtlch\fcs1 
\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape sprecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, t_mtrlnt *tbc) 
\hich\f1 \endash \loch\f1  Space unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 forward one record.  The size of the record is returned in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_sprecr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr, t_mtrlnt *tbc) 
\hich\f1 \endash \hich\af1\dbch\af31505\loch\f1  Space unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 reverse one record.  The size of the record is returned in tbc.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrtmk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Write a tape mark on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wreom}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Write an end-of-medium marker on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (this effectively erases the rest of the tape).
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrgap}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 (UNIT *uptr, uint32 gaplen, uint32 bpi) \hich\f1 \endash \loch\f1  Write an erase gap on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 gaplen}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 tenths of an inch in length at a tape density of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 bpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  bits per inch.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_rewind}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *u
\hich\af1\dbch\af31505\loch\f1 ptr) \hich\f1 \endash \loch\f1  Rewind unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
.  This operation succeeds whether or not the unit is attached to a file.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Reset unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  This routine should be called when a tape unit is reset.

\par 
\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_bot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Return TRU\hich\af1\dbch\af31505\loch\f1 E if unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 is at beginning-of-tape.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape wrp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Return TRUE if unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is write-protected.
\par 
\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_eot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (UNIT *uptr) \hich\f1 \endash 
\loch\f1  Return TRUE if unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 has exceed the capacity specified of the specified unit (kept in uptr->cap\hich\af1\dbch\af31505\loch\f1 ac).
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Sim_tape_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_tape_detach, sim_tape_set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
sim_tape_show_fmt, sim_tape_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_capac}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  return standard SCP status codes; the other magtape library routines return return private codes for success and failure.  The currentl\hich\af1\dbch\af31505\loch\f1 
y defined magtape status codes are:
\par 
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_OK\tab \tab operation successful
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_UNATT\tab \tab unit is not attached to a file
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_FMT\tab \tab unit specifies an unsupported tape file format
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_IOERR\tab \tab host operating system I/O error during operation
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_INVRL\tab \tab invalid rec\hich\af1\dbch\af31505\loch\f1 ord length (exceeds maximum allowed)
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_RECE\tab \tab record header contains error flag
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_TMK\tab \tab tape mark encountered
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_BOT\tab \tab beginning of tape encountered during reverse operation
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_EOM\tab \tab end of medium encountered
\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_WRP\tab \tab write protected unit durin\hich\af1\dbch\af31505\loch\f1 g write operation
\par 
\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Sim_tape_set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_tape_show_fmt, sim_tape_set_capac, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  should be referenced by an entry in the tape device\hich\f1 \rquote \loch\f1 s modifier list, as follows:
\par 
\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 MTAB tape_mod[] = \{
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  MTAB_XTD|MTAB_VDV, 0, \'93\loch\f2 \hich\f2 FORMAT\'94\loch\f2 
\hich\f2 , \'93\loch\f2 \hich\f2 FORMAT\'94,
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2   \tab \hich\af2\dbch\af31505\loch\f2   &sim_tape_set_fmt, &sim_tape_show_fmt, NULL \}
,
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2  MTAB_XTD|MTAB_VUN, 0, \'93\loch\f2 \hich\f2 CAPACITY\'94\loch\f2 
\hich\f2 , \'93\loch\f2 \hich\f2 CAPACITY\'94,
\par }\pard \ltrpar\ql \li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2   &sim_tape_set_capac, &sim_tape_show_capac, NULL \}\hich\f2 , \'85
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \}\hich\af2\dbch\af31505\loch\f2 ;
\par {\*\bkmkstart _Toc215048100}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af1 \ltrch\fcs0 \b\i\f1 \hich\af1\dbch\af31505\loch\f1 6.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar
\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Breakpoint Support{\*\bkmkend _Toc215048100}
\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 SCP provides underlying mechanisms to track multipl\hich\af1\dbch\af31505\loch\f1 e breakpoints of different types.  Most VM\hich\f1 \rquote \loch\f1 
s implement at least instruction execution breakpoints (type E); but a VM might also allow for break on read (type R), write (type W), and so on.  Up to 26 different breakpoint types, identified by the letters A \hich\af1\dbch\af31505\loch\f1 t
\hich\af1\dbch\af31505\loch\f1 hrough Z, are supported.
\par 
\par \hich\af1\dbch\af31505\loch\f1 The VM interface to the breakpoint package consists of three variables and one subroutine:
\par 
\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 
\ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_types}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1  \hich\f1 \endash \loch\f1 
 initialized by the VM (usually in the CPU reset routine) to a mask of all supported breakpoints.
\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_dflt}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  \hich\f1 \endash \loch\f1  initiali\hich\af1\dbch\af31505\loch\f1 zed by the VM to the mask for the default breakpoint type.
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1  \hich\f1 \endash \loch\f1  maintained by SCP, providing a bit mask summary of whether any breakpoints of a particular type have been defined.
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 If the VM only implements one type of breakpoint, then }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_su\hich\af1\dbch\af31505\loch\f1 mm}{\rtlch\fcs1 \af1 \ltrch\fcs0 
\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is non-zero if any breakpoints are set.
\par 
\par \hich\af1\dbch\af31505\loch\f1 To test whether a breakpoint of particular type is set for an address, the VM calls
\par 
\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uint32l }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 sim_brk_test}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  (t_addr addr, int32 typ) \hich\f1 \endash \loch\f1  test to see if a breakpoint of type }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 
\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 typ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  is set for location }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{
\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ; returns 0 if \hich\af1\dbch\af31505\loch\f1 no, and a bit mask of all breakpoints that match typ if yes
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 Because }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_test}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 
 can be a lengthy procedure, it is usually prefaced with a test of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :
\par 
\par \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 if (sim_brk_summ && sim_brk_test (PC, SWMASK (\hich\f2 \lquote \loch\f2 E\hich\f2 \rquote \loch\f2 ))) \{
\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 <execution break> \}
\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par \hich\af1\dbch\af31505\loch\f1 
To accommodate more complex breakpoint schemes, SCP implements a concept of breakpoint spaces.  Each breakpoint space is an orthogonal collection of breakpoints that are tracked independently.  For example, in a symmetric multiprocessing simulation, break
\hich\af1\dbch\af31505\loch\f1 p\hich\af1\dbch\af31505\loch\f1 
oint spaces could be assigned to each CPU to distinguish E (execution) breakpoints for different processors.  SCP supports up to 64 breakpoint spaces; the space is specified by bits <31:26> of the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 
\hich\af1\dbch\af31505\loch\f1 typ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1  argument to }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_test}{\rtlch\fcs1 \af1 
\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 .  By default, there is only on\hich\af1\dbch\af31505\loch\f1 e breakpoint space (space 0).
\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 
\par }{\*\themedata 504b030414000600080000002100e9de0fbfff0000001c020000130000005b436f6e74656e745f54797065735d2e786d6cac91cb4ec3301045f748fc83e52d4a
9cb2400825e982c78ec7a27cc0c8992416c9d8b2a755fbf74cd25442a820166c2cd933f79e3be372bd1f07b5c3989ca74aaff2422b24eb1b475da5df374fd9ad
5689811a183c61a50f98f4babebc2837878049899a52a57be670674cb23d8e90721f90a4d2fa3802cb35762680fd800ecd7551dc18eb899138e3c943d7e503b6
b01d583deee5f99824e290b4ba3f364eac4a430883b3c092d4eca8f946c916422ecab927f52ea42b89a1cd59c254f919b0e85e6535d135a8de20f20b8c12c3b0
0c895fcf6720192de6bf3b9e89ecdbd6596cbcdd8eb28e7c365ecc4ec1ff1460f53fe813d3cc7f5b7f020000ffff0300504b030414000600080000002100a5d6
a7e7c0000000360100000b0000005f72656c732f2e72656c73848fcf6ac3300c87ef85bd83d17d51d2c31825762fa590432fa37d00e1287f68221bdb1bebdb4f
c7060abb0884a4eff7a93dfeae8bf9e194e720169aaa06c3e2433fcb68e1763dbf7f82c985a4a725085b787086a37bdbb55fbc50d1a33ccd311ba548b6309512
0f88d94fbc52ae4264d1c910d24a45db3462247fa791715fd71f989e19e0364cd3f51652d73760ae8fa8c9ffb3c330cc9e4fc17faf2ce545046e37944c69e462
a1a82fe353bd90a865aad41ed0b5b8f9d6fd010000ffff0300504b0304140006000800000021006b799616830000008a0000001c0000007468656d652f746865
6d652f7468656d654d616e616765722e786d6c0ccc4d0ac3201040e17da17790d93763bb284562b2cbaebbf600439c1a41c7a0d29fdbd7e5e38337cedf14d59b
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