lib/asm-docs/arm32.ts

// Copyright (c) 2021, Compiler Explorer Authors
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import { AssemblyInstructionInfo, BaseAssemblyDocumentationProvider } from './base';
import { getAsmOpcode } from './generated/asm-docs-arm32';

export class Arm32DocumentationProvider extends BaseAssemblyDocumentationProvider {
    private static readonly CONDITIONAL_INSTRUCTION_REGEXP = /^([A-Za-z]+?)(EQ|NE|CS|CC|MI|PL|VS|VC|HI|LS|GE|LT|GT|LE|AL)$/;
    public static get key() { return 'arm32'; }
    public override getInstructionInformation(instruction: string): AssemblyInstructionInfo | null {
        const info = getAsmOpcode(instruction) || Arm32DocumentationProvider.getConditionalOpcode(instruction);
        return info || null;
    }

    private static readonly CONDITIONAL_OPCODE_TAGS: Record<string, string> = {
        EQ: 'If equal, ',
        NE: 'If not equal, ',
        CS: 'If carry set, ',
        CC: 'If carry clear, ',
        MI: 'If negative, ',
        PL: 'If positive or zero, ',
        VS: 'If overflow, ',
        VC: 'If no overflow, ',
        HI: 'If unsigned higher, ',
        LS: 'If unsigned lower or same, ',
        GE: 'If signed greater than or equal, ',
        LT: 'If signed less than, ',
        GT: 'If signed greater than, ',
        LE: 'If signed less than or equal, ',
    };

    /** Add additional notes for conditional instructions */
    private static getConditionalOpcode(instruction: string): AssemblyInstructionInfo | null {
        // If the instruction is a conditional instruction
        const isConditionalOpcode = instruction.match(Arm32DocumentationProvider.CONDITIONAL_INSTRUCTION_REGEXP);
        if (!isConditionalOpcode) {
            return null;
        }
        const information = getAsmOpcode(isConditionalOpcode[1]);
        const text = Arm32DocumentationProvider.CONDITIONAL_OPCODE_TAGS[isConditionalOpcode[2]] || '';
        return {
            ...information,
            tooltip: text + information.tooltip,
            html: text + information.html,
        };
    }
}