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| <title>XGETBV—Get Value of Extended Control Register </title></head> |
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| <h1>XGETBV—Get Value of Extended Control Register</h1> |
| <table> |
| <tr> |
| <th>Opcode</th> |
| <th>Instruction</th> |
| <th>Op/En</th> |
| <th>64-Bit Mode</th> |
| <th>Compat/Leg Mode</th> |
| <th>Description</th></tr> |
| <tr> |
| <td>0F 01 D0</td> |
| <td>XGETBV</td> |
| <td>NP</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Reads an XCR specified by ECX into EDX:EAX.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>NP</td> |
| <td>NA</td> |
| <td>NA</td> |
| <td>NA</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Reads the contents of the extended control register (XCR) specified in the ECX register into registers EDX:EAX. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register is loaded with the high-order 32 bits of the XCR and the EAX register is loaded with the low-order 32 bits. (On proces-sors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If fewer than 64 bits are implemented in the XCR being read, the values returned to EDX:EAX in unimplemented bit loca-tions are undefined.</p> |
| <p>XCR0 is supported on any processor that supports the XGETBV instruction. If CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 1, executing XGETBV with ECX = 1 returns in EDX:EAX the logical-AND of XCR0 and the current value of the XINUSE state-component bitmap. This allows software to discover the state of the init optimization used by XSAVEOPT and XSAVES. See Chapter 13, “Managing State Using the XSAVE Feature Set‚” in <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1</em>.</p> |
| <p>Use of any other value for ECX results in a general-protection (#GP) exception.</p> |
| <h2>Operation</h2> |
| <pre>EDX:EAX ← XCR[ECX];</pre> |
| <h2>Flags Affected</h2> |
| <p>None.</p> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>XGETBV:</p> |
| <p>unsigned __int64 _xgetbv( unsigned int);</p> |
| <h2>Protected Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If an invalid XCR is specified in ECX (includes ECX = 1 if CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 0).</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If CPUID.01H:ECX.XSAVE[bit 26] = 0.</p> |
| <p>If CR4.OSXSAVE[bit 18] = 0.</p> |
| <p>If the LOCK prefix is used.</p> |
| <p>If 66H, F3H or F2H prefix is used.</p></td></tr></table> |
| <h2>Real-Address Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If an invalid XCR is specified in ECX (includes ECX = 1 if CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 0).</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If CPUID.01H:ECX.XSAVE[bit 26] = 0.</p> |
| <p>If CR4.OSXSAVE[bit 18] = 0.</p> |
| <p>If the LOCK prefix is used.</p> |
| <p>If 66H, F3H or F2H prefix is used.</p></td></tr></table> |
| <h2>Virtual-8086 Mode Exceptions</h2> |
| <p>Same exceptions as in protected mode.</p> |
| <h2>Compatibility Mode Exceptions</h2> |
| <p>Same exceptions as in protected mode.</p> |
| <h2>64-Bit Mode Exceptions</h2> |
| <p>Same exceptions as in protected mode.</p></body></html> |