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 <title>WRMSR—Write to Model Specific Register </title></head>
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 <h1>WRMSR—Write to Model Specific Register</h1>
 <table>
 <tr>
 <th>Opcode</th>
 <th>Instruction</th>
 <th>Op/En</th>
 <th>64-Bit Mode</th>
 <th>Compat/Leg Mode</th>
 <th>Description</th></tr>
 <tr>
 <td>0F 30</td>
 <td>WRMSR</td>
 <td>NP</td>
 <td>Valid</td>
 <td>Valid</td>
 <td>Write the value in EDX:EAX to MSR specified by ECX.</td></tr></table>
 <h3>Instruction Operand Encoding</h3>
 <table>
 <tr>
 <td>Op/En</td>
 <td>Operand 1</td>
 <td>Operand 2</td>
 <td>Operand 3</td>
 <td>Operand 4</td></tr>
 <tr>
 <td>NP</td>
 <td>NA</td>
 <td>NA</td>
 <td>NA</td>
 <td>NA</td></tr></table>
 <h2>Description</h2>
 <p>Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of the EDX register are copied to high-order 32 bits of the selected MSR and the contents of the EAX register are copied to low-order 32 bits of the MSR. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an MSR should be set to values previously read.</p>
 <p>This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) is generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception. The processor will also generate a general protection exception if software attempts to write to bits in a reserved MSR.</p>
 <p>When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated. This includes global entries (see “Translation Lookaside Buffers (TLBs)” in Chapter 3 of the <em>Intel® 64 and IA-32 Architectures Software Devel-oper’s Manual, Volume 3A</em>).</p>
 <p>MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors. Chapter 35, “Model-Specific Registers (MSRs)”, in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C</em>, lists all MSRs that can be written with this instruction and their addresses. Note that each processor family has its own set of MSRs.</p>
 <p>The WRMSR instruction is a serializing instruction (see “Serializing Instructions” in Chapter 8 of the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>). Note that WRMSR to the IA32_TSC_DEADLINE MSR (MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.</p>
 <p>The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before using this instruction.</p>
 <h2>IA-32 Architecture Compatibility</h2>
 <p>The MSRs and the ability to read them with the WRMSR instruction were introduced into the IA-32 architecture with the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor results in an invalid opcode exception #UD.</p>
 <h2>Operation</h2>
 <pre>MSR[ECX] ← EDX:EAX;</pre>
 <h2>Flags Affected</h2>
 <p>None.</p>
 <h2>Protected Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP(0)</td>
 <td>
 <p>If the current privilege level is not 0.</p>
 <p>If the value in ECX specifies a reserved or unimplemented MSR address.</p>
 <p>If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.</p>
 <p>If the source register contains a non-canonical address and ECX specifies one of the following MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_LSTAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.</p></td></tr>
 <tr>
 <td>#UD</td>
 <td>If the LOCK prefix is used.</td></tr></table>
 <h2>Real-Address Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP</td>
 <td>
 <p>If the value in ECX specifies a reserved or unimplemented MSR address.</p>
 <p>If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.</p>
 <p>If the source register contains a non-canonical address and ECX specifies one of the following MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_LSTAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.</p></td></tr>
 <tr>
 <td>#UD</td>
 <td>If the LOCK prefix is used.</td></tr></table>
 <h2>Virtual-8086 Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP(0)</td>
 <td> The WRMSR instruction is not recognized in virtual-8086 mode.</td></tr></table>
 <h2>Compatibility Mode Exceptions</h2>
 <p>Same exceptions as in protected mode.</p>
 <h2>64-Bit Mode Exceptions</h2>
 <p>Same exceptions as in protected mode.</p></body></html>
	<!DOCTYPE html>

	<html>
	<head>
	<meta charset="UTF-8">
	<link href="style.css" type="text/css" rel="stylesheet">
	<title>WRMSR—Write to Model Specific Register </title></head>
	<body>
	<h1>WRMSR—Write to Model Specific Register</h1>
	<table>
	<tr>
	<th>Opcode</th>
	<th>Instruction</th>
	<th>Op/En</th>
	<th>64-Bit Mode</th>
	<th>Compat/Leg Mode</th>
	<th>Description</th></tr>
	<tr>
	<td>0F 30</td>
	<td>WRMSR</td>
	<td>NP</td>
	<td>Valid</td>
	<td>Valid</td>
	<td>Write the value in EDX:EAX to MSR specified by ECX.</td></tr></table>
	<h3>Instruction Operand Encoding</h3>
	<table>
	<tr>
	<td>Op/En</td>
	<td>Operand 1</td>
	<td>Operand 2</td>
	<td>Operand 3</td>
	<td>Operand 4</td></tr>
	<tr>
	<td>NP</td>
	<td>NA</td>
	<td>NA</td>
	<td>NA</td>
	<td>NA</td></tr></table>
	<h2>Description</h2>
	<p>Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of the EDX register are copied to high-order 32 bits of the selected MSR and the contents of the EAX register are copied to low-order 32 bits of the MSR. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an MSR should be set to values previously read.</p>
	<p>This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) is generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception. The processor will also generate a general protection exception if software attempts to write to bits in a reserved MSR.</p>
	<p>When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated. This includes global entries (see “Translation Lookaside Buffers (TLBs)” in Chapter 3 of the <em>Intel® 64 and IA-32 Architectures Software Devel-oper’s Manual, Volume 3A</em>).</p>
	<p>MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors. Chapter 35, “Model-Specific Registers (MSRs)”, in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C</em>, lists all MSRs that can be written with this instruction and their addresses. Note that each processor family has its own set of MSRs.</p>
	<p>The WRMSR instruction is a serializing instruction (see “Serializing Instructions” in Chapter 8 of the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>). Note that WRMSR to the IA32_TSC_DEADLINE MSR (MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.</p>
	<p>The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before using this instruction.</p>
	<h2>IA-32 Architecture Compatibility</h2>
	<p>The MSRs and the ability to read them with the WRMSR instruction were introduced into the IA-32 architecture with the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor results in an invalid opcode exception #UD.</p>
	<h2>Operation</h2>
	<pre>MSR[ECX] ← EDX:EAX;</pre>
	<h2>Flags Affected</h2>
	<p>None.</p>
	<h2>Protected Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP(0)</td>
	<td>
	<p>If the current privilege level is not 0.</p>
	<p>If the value in ECX specifies a reserved or unimplemented MSR address.</p>
	<p>If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.</p>
	<p>If the source register contains a non-canonical address and ECX specifies one of the following MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_LSTAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.</p></td></tr>
	<tr>
	<td>#UD</td>
	<td>If the LOCK prefix is used.</td></tr></table>
	<h2>Real-Address Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP</td>
	<td>
	<p>If the value in ECX specifies a reserved or unimplemented MSR address.</p>
	<p>If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.</p>
	<p>If the source register contains a non-canonical address and ECX specifies one of the following MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_LSTAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.</p></td></tr>
	<tr>
	<td>#UD</td>
	<td>If the LOCK prefix is used.</td></tr></table>
	<h2>Virtual-8086 Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP(0)</td>
	<td> The WRMSR instruction is not recognized in virtual-8086 mode.</td></tr></table>
	<h2>Compatibility Mode Exceptions</h2>
	<p>Same exceptions as in protected mode.</p>
	<h2>64-Bit Mode Exceptions</h2>
	<p>Same exceptions as in protected mode.</p></body></html>