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| <title>VZEROALL—Zero All YMM Registers </title></head> |
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| <h1>VZEROALL—Zero All YMM Registers</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 bit Mode Support</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>VEX.256.0F.WIG 77</p> |
| <p>VZEROALL</p></td> |
| <td>NP</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Zero all YMM registers.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>NP</td> |
| <td>NA</td> |
| <td>NA</td> |
| <td>NA</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>The instruction zeros contents of all XMM or YMM registers.</p> |
| <p>Note: VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. In Compatibility and legacy 32-bit mode only the lower 8 registers are modified.</p> |
| <h2>Operation</h2> |
| <p><strong>VZEROALL (VEX.256 encoded version)</strong></p> |
| <pre>IF (64-bit mode) |
| YMM0[VLMAX-1:0] ← 0 |
| YMM1[VLMAX-1:0] ← 0 |
| YMM2[VLMAX-1:0] ← 0 |
| YMM3[VLMAX-1:0] ← 0 |
| YMM4[VLMAX-1:0] ← 0 |
| YMM5[VLMAX-1:0] ← 0 |
| YMM6[VLMAX-1:0] ← 0 |
| YMM7[VLMAX-1:0] ← 0 |
| YMM8[VLMAX-1:0] ← 0 |
| YMM9[VLMAX-1:0] ← 0 |
| YMM10[VLMAX-1:0] ← 0 |
| YMM11[VLMAX-1:0] ← 0 |
| YMM12[VLMAX-1:0] ← 0 |
| YMM13[VLMAX-1:0] ← 0 |
| YMM14[VLMAX-1:0] ← 0 |
| YMM15[VLMAX-1:0] ← 0 |
| ELSE |
| YMM0[VLMAX-1:0] ← 0 |
| YMM1[VLMAX-1:0] ← 0 |
| YMM2[VLMAX-1:0] ← 0 |
| YMM3[VLMAX-1:0] ← 0 |
| YMM4[VLMAX-1:0] ← 0 |
| YMM5[VLMAX-1:0] ← 0 |
| YMM6[VLMAX-1:0] ← 0 |
| YMM7[VLMAX-1:0] ← 0 |
| YMM8-15: Unmodified |
| FI</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>VZEROALL:</p> |
| <p> _mm256_zeroall()</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>None.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 8.</p></body></html> |