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 <title>VPERMILPD — Permute Double-Precision Floating-Point Values </title></head>
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 <h1>VPERMILPD — Permute Double-Precision Floating-Point Values</h1>
 <table>
 <tr>
 <th>Opcode/Instruction</th>
 <th>Op/En</th>
 <th>64/32 bit Mode Support</th>
 <th>CPUID Feature Flag</th>
 <th>Description</th></tr>
 <tr>
 <td>VEX.NDS.128.66.0F38.W0 0D /r VPERMILPD <em>xmm1, xmm2, xmm3/m128</em></td>
 <td>RVM</td>
 <td>V/V</td>
 <td>AVX</td>
 <td>Permute double-precision floating-point values in <em>xmm2</em> using controls from <em>xmm3/mem</em> and store result in <em>xmm1</em>.</td></tr>
 <tr>
 <td>VEX.NDS.256.66.0F38.W0 0D /r VPERMILPD <em>ymm1, ymm2, ymm3/m256</em></td>
 <td>RVM</td>
 <td>V/V</td>
 <td>AVX</td>
 <td>Permute double-precision floating-point values in <em>ymm2</em> using controls from <em>ymm3/mem</em> and store result in <em>ymm1</em>.</td></tr>
 <tr>
 <td>VEX.128.66.0F3A.W0 05 /r ib VPERMILPD <em>xmm1, xmm2/m128, imm8</em></td>
 <td>RMI</td>
 <td>V/V</td>
 <td>AVX</td>
 <td>Permute double-precision floating-point values in <em>xmm2/mem </em>using controls from <em>imm8</em>.</td></tr>
 <tr>
 <td>VEX.256.66.0F3A.W0 05 /r ib VPERMILPD <em>ymm1, ymm2/m256, imm8</em></td>
 <td>RMI</td>
 <td>V/V</td>
 <td>AVX</td>
 <td>Permute double-precision floating-point values in <em>ymm2/mem</em> using controls from <em>imm8</em>.</td></tr></table>
 <h3>Instruction Operand Encoding</h3>
 <table>
 <tr>
 <td>Op/En</td>
 <td>Operand 1</td>
 <td>Operand 2</td>
 <td>Operand 3</td>
 <td>Operand 4</td></tr>
 <tr>
 <td>RVM</td>
 <td>ModRM:reg (w)</td>
 <td>VEX.vvvv (r)</td>
 <td>ModRM:r/m (r)</td>
 <td>NA</td></tr>
 <tr>
 <td>RMI</td>
 <td>ModRM:reg (w)</td>
 <td>ModRM:r/m (r)</td>
 <td>imm8</td>
 <td>NA</td></tr></table>
 <h2>Description</h2>
 <p>Permute double-precision floating-point values in the first source operand (second operand) using 8-bit control fields in the low bytes of the second source operand (third operand) and store results in the destination operand (first operand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit memory location, and the destination operand is a YMM register.</p>
 <p>X3</p>
 <p>X2</p>
 <p>X1</p>
 <p>X0</p>
 <p>SRC1</p>
 <p>X2..X3</p>
 <p>X2..X3</p>
 <p>X0..X1</p>
 <p>DEST</p>
 <h3>Figure 4-38.  VPERMILPD operation</h3>
 <p>There is one control byte per destination double-precision element. Each control byte is aligned with the low 8 bits of the corresponding double-precision destination element. Each control byte contains a 1-bit select field (see Figure 4-39) that determines which of the source elements are selected. Source elements are restricted to lie in the same source 128-bit region as the destination.</p>
 <p>Bit</p>
 <p>66</p>
 <p>1</p>
 <p>194 193</p>
 <p>65</p>
 <p>2</p>
 <p>127</p>
 <p>255</p>
 <p>63</p>
 <p><strong>. . .</strong></p>
 <p>d</p>
 <p>d</p>
 <p>d</p>
 <p>ignored</p>
 <p>ignored</p>
 <p>ignored</p>
 <p>sel</p>
 <p>sel</p>
 <p>sel</p>
 <p>e</p>
 <p>e</p>
 <p>e</p>
 <p>r</p>
 <p>r</p>
 <p>r</p>
 <p>o</p>
 <p>o</p>
 <p>o</p>
 <p>n</p>
 <p>n</p>
 <p>n</p>
 <p>g</p>
 <p>g</p>
 <p>g</p>
 <p>i</p>
 <p>i</p>
 <p>i</p>
 <p>Control Field 4</p>
 <p>Control Field 2</p>
 <p>Control Field1</p>
 <h3>Figure 4-39.  VPERMILPD Shuffle Control</h3>
 <p>(immediate control version)</p>
 <p>Permute double-precision floating-point values in the first source operand (second operand) using two, 1-bit control fields in the low 2 bits of the 8-bit immediate and store results in the destination operand (first operand). The source operand is a YMM register or 256-bit memory location and the destination operand is a YMM register.</p>
 <p>Note: For the VEX.128.66.0F3A 05 instruction version, VEX.vvvv is reserved and must be 1111b otherwise instruc-tion will #UD.</p>
 <p>Note: For the VEX.256.66.0F3A 05 instruction version, VEX.vvvv is reserved and must be 1111b otherwise instruc-tion will #UD.</p>
 <h2>Operation</h2>
 <p><strong>VPERMILPD (256-bit immediate version)</strong></p>
 <pre>IF (imm8[0] = 0) THEN DEST[63:0]←SRC1[63:0]
 IF (imm8[0] = 1) THEN DEST[63:0]←SRC1[127:64]
 IF (imm8[1] = 0) THEN DEST[127:64]←SRC1[63:0]
 IF (imm8[1] = 1) THEN DEST[127:64]←SRC1[127:64]
 IF (imm8[2] = 0) THEN DEST[191:128]←SRC1[191:128]
 IF (imm8[2] = 1) THEN DEST[191:128]←SRC1[255:192]
 IF (imm8[3] = 0) THEN DEST[255:192]←SRC1[191:128]
 IF (imm8[3] = 1) THEN DEST[255:192]←SRC1[255:192]</pre>
 <p><strong>VPERMILPD (128-bit immediate version)</strong></p>
 <pre>IF (imm8[0] = 0) THEN DEST[63:0]←SRC1[63:0]
 IF (imm8[0] = 1) THEN DEST[63:0]←SRC1[127:64]
 IF (imm8[1] = 0) THEN DEST[127:64]←SRC1[63:0]
 IF (imm8[1] = 1) THEN DEST[127:64]←SRC1[127:64]
 DEST[VLMAX-1:128] ← 0</pre>
 <p><strong>VPERMILPD (256-bit variable version)</strong></p>
 <pre>IF (SRC2[1] = 0) THEN DEST[63:0]←SRC1[63:0]
 IF (SRC2[1] = 1) THEN DEST[63:0]←SRC1[127:64]
 IF (SRC2[65] = 0) THEN DEST[127:64]←SRC1[63:0]
 IF (SRC2[65] = 1) THEN DEST[127:64]←SRC1[127:64]
 IF (SRC2[129] = 0) THEN DEST[191:128]←SRC1[191:128]
 IF (SRC2[129] = 1) THEN DEST[191:128]←SRC1[255:192]
 IF (SRC2[193] = 0) THEN DEST[255:192]←SRC1[191:128]
 IF (SRC2[193] = 1) THEN DEST[255:192]←SRC1[255:192]</pre>
 <p><strong>VPERMILPD (128-bit variable version)</strong></p>
 <pre>IF (SRC2[1] = 0) THEN DEST[63:0]←SRC1[63:0]
 IF (SRC2[1] = 1) THEN DEST[63:0]←SRC1[127:64]
 IF (SRC2[65] = 0) THEN DEST[127:64]←SRC1[63:0]
 IF (SRC2[65] = 1) THEN DEST[127:64]←SRC1[127:64]
 DEST[VLMAX-1:128] ← 0</pre>
 <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
 <p>VPERMILPD:</p>
 <p> __m128d _mm_permute_pd (__m128d a, int control)</p>
 <p>VPERMILPD:</p>
 <p> __m256d _mm256_permute_pd (__m256d a, int control)</p>
 <p>VPERMILPD:</p>
 <p> __m128d _mm_permutevar_pd (__m128d a, __m128i control);</p>
 <p>VPERMILPD:</p>
 <p> __m256d _mm256_permutevar_pd (__m256d a, __m256i control);</p>
 <h2>SIMD Floating-Point Exceptions</h2>
 <p>None.</p>
 <h2>Other Exceptions</h2>
 <p>See Exceptions Type 6; additionally</p>
 <table class="exception-table">
 <tr>
 <td>#UD</td>
 <td>If VEX.W = 1</td></tr></table></body></html>
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	<html>
	<head>
	<meta charset="UTF-8">
	<link href="style.css" type="text/css" rel="stylesheet">
	<title>VPERMILPD — Permute Double-Precision Floating-Point Values </title></head>
	<body>
	<h1>VPERMILPD — Permute Double-Precision Floating-Point Values</h1>
	<table>
	<tr>
	<th>Opcode/Instruction</th>
	<th>Op/En</th>
	<th>64/32 bit Mode Support</th>
	<th>CPUID Feature Flag</th>
	<th>Description</th></tr>
	<tr>
	<td>VEX.NDS.128.66.0F38.W0 0D /r VPERMILPD <em>xmm1, xmm2, xmm3/m128</em></td>
	<td>RVM</td>
	<td>V/V</td>
	<td>AVX</td>
	<td>Permute double-precision floating-point values in <em>xmm2</em> using controls from <em>xmm3/mem</em> and store result in <em>xmm1</em>.</td></tr>
	<tr>
	<td>VEX.NDS.256.66.0F38.W0 0D /r VPERMILPD <em>ymm1, ymm2, ymm3/m256</em></td>
	<td>RVM</td>
	<td>V/V</td>
	<td>AVX</td>
	<td>Permute double-precision floating-point values in <em>ymm2</em> using controls from <em>ymm3/mem</em> and store result in <em>ymm1</em>.</td></tr>
	<tr>
	<td>VEX.128.66.0F3A.W0 05 /r ib VPERMILPD <em>xmm1, xmm2/m128, imm8</em></td>
	<td>RMI</td>
	<td>V/V</td>
	<td>AVX</td>
	<td>Permute double-precision floating-point values in <em>xmm2/mem </em>using controls from <em>imm8</em>.</td></tr>
	<tr>
	<td>VEX.256.66.0F3A.W0 05 /r ib VPERMILPD <em>ymm1, ymm2/m256, imm8</em></td>
	<td>RMI</td>
	<td>V/V</td>
	<td>AVX</td>
	<td>Permute double-precision floating-point values in <em>ymm2/mem</em> using controls from <em>imm8</em>.</td></tr></table>
	<h3>Instruction Operand Encoding</h3>
	<table>
	<tr>
	<td>Op/En</td>
	<td>Operand 1</td>
	<td>Operand 2</td>
	<td>Operand 3</td>
	<td>Operand 4</td></tr>
	<tr>
	<td>RVM</td>
	<td>ModRM:reg (w)</td>
	<td>VEX.vvvv (r)</td>
	<td>ModRM:r/m (r)</td>
	<td>NA</td></tr>
	<tr>
	<td>RMI</td>
	<td>ModRM:reg (w)</td>
	<td>ModRM:r/m (r)</td>
	<td>imm8</td>
	<td>NA</td></tr></table>
	<h2>Description</h2>
	<p>Permute double-precision floating-point values in the first source operand (second operand) using 8-bit control fields in the low bytes of the second source operand (third operand) and store results in the destination operand (first operand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit memory location, and the destination operand is a YMM register.</p>
	<p>X3</p>
	<p>X2</p>
	<p>X1</p>
	<p>X0</p>
	<p>SRC1</p>
	<p>X2..X3</p>
	<p>X2..X3</p>
	<p>X0..X1</p>
	<p>DEST</p>
	<h3>Figure 4-38. VPERMILPD operation</h3>
	<p>There is one control byte per destination double-precision element. Each control byte is aligned with the low 8 bits of the corresponding double-precision destination element. Each control byte contains a 1-bit select field (see Figure 4-39) that determines which of the source elements are selected. Source elements are restricted to lie in the same source 128-bit region as the destination.</p>
	<p>Bit</p>
	<p>66</p>
	<p>1</p>
	<p>194 193</p>
	<p>65</p>
	<p>2</p>
	<p>127</p>
	<p>255</p>
	<p>63</p>
	<p><strong>. . .</strong></p>
	<p>d</p>
	<p>d</p>
	<p>d</p>
	<p>ignored</p>
	<p>ignored</p>
	<p>ignored</p>
	<p>sel</p>
	<p>sel</p>
	<p>sel</p>
	<p>e</p>
	<p>e</p>
	<p>e</p>
	<p>r</p>
	<p>r</p>
	<p>r</p>
	<p>o</p>
	<p>o</p>
	<p>o</p>
	<p>n</p>
	<p>n</p>
	<p>n</p>
	<p>g</p>
	<p>g</p>
	<p>g</p>
	<p>i</p>
	<p>i</p>
	<p>i</p>
	<p>Control Field 4</p>
	<p>Control Field 2</p>
	<p>Control Field1</p>
	<h3>Figure 4-39. VPERMILPD Shuffle Control</h3>
	<p>(immediate control version)</p>
	<p>Permute double-precision floating-point values in the first source operand (second operand) using two, 1-bit control fields in the low 2 bits of the 8-bit immediate and store results in the destination operand (first operand). The source operand is a YMM register or 256-bit memory location and the destination operand is a YMM register.</p>
	<p>Note: For the VEX.128.66.0F3A 05 instruction version, VEX.vvvv is reserved and must be 1111b otherwise instruc-tion will #UD.</p>
	<p>Note: For the VEX.256.66.0F3A 05 instruction version, VEX.vvvv is reserved and must be 1111b otherwise instruc-tion will #UD.</p>
	<h2>Operation</h2>
	<p><strong>VPERMILPD (256-bit immediate version)</strong></p>
	<pre>IF (imm8[0] = 0) THEN DEST[63:0]←SRC1[63:0]
	IF (imm8[0] = 1) THEN DEST[63:0]←SRC1[127:64]
	IF (imm8[1] = 0) THEN DEST[127:64]←SRC1[63:0]
	IF (imm8[1] = 1) THEN DEST[127:64]←SRC1[127:64]
	IF (imm8[2] = 0) THEN DEST[191:128]←SRC1[191:128]
	IF (imm8[2] = 1) THEN DEST[191:128]←SRC1[255:192]
	IF (imm8[3] = 0) THEN DEST[255:192]←SRC1[191:128]
	IF (imm8[3] = 1) THEN DEST[255:192]←SRC1[255:192]</pre>
	<p><strong>VPERMILPD (128-bit immediate version)</strong></p>
	<pre>IF (imm8[0] = 0) THEN DEST[63:0]←SRC1[63:0]
	IF (imm8[0] = 1) THEN DEST[63:0]←SRC1[127:64]
	IF (imm8[1] = 0) THEN DEST[127:64]←SRC1[63:0]
	IF (imm8[1] = 1) THEN DEST[127:64]←SRC1[127:64]
	DEST[VLMAX-1:128] ← 0</pre>
	<p><strong>VPERMILPD (256-bit variable version)</strong></p>
	<pre>IF (SRC2[1] = 0) THEN DEST[63:0]←SRC1[63:0]
	IF (SRC2[1] = 1) THEN DEST[63:0]←SRC1[127:64]
	IF (SRC2[65] = 0) THEN DEST[127:64]←SRC1[63:0]
	IF (SRC2[65] = 1) THEN DEST[127:64]←SRC1[127:64]
	IF (SRC2[129] = 0) THEN DEST[191:128]←SRC1[191:128]
	IF (SRC2[129] = 1) THEN DEST[191:128]←SRC1[255:192]
	IF (SRC2[193] = 0) THEN DEST[255:192]←SRC1[191:128]
	IF (SRC2[193] = 1) THEN DEST[255:192]←SRC1[255:192]</pre>
	<p><strong>VPERMILPD (128-bit variable version)</strong></p>
	<pre>IF (SRC2[1] = 0) THEN DEST[63:0]←SRC1[63:0]
	IF (SRC2[1] = 1) THEN DEST[63:0]←SRC1[127:64]
	IF (SRC2[65] = 0) THEN DEST[127:64]←SRC1[63:0]
	IF (SRC2[65] = 1) THEN DEST[127:64]←SRC1[127:64]
	DEST[VLMAX-1:128] ← 0</pre>
	<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
	<p>VPERMILPD:</p>
	<p> __m128d _mm_permute_pd (__m128d a, int control)</p>
	<p>VPERMILPD:</p>
	<p> __m256d _mm256_permute_pd (__m256d a, int control)</p>
	<p>VPERMILPD:</p>
	<p> __m128d _mm_permutevar_pd (__m128d a, __m128i control);</p>
	<p>VPERMILPD:</p>
	<p> __m256d _mm256_permutevar_pd (__m256d a, __m256i control);</p>
	<h2>SIMD Floating-Point Exceptions</h2>
	<p>None.</p>
	<h2>Other Exceptions</h2>
	<p>See Exceptions Type 6; additionally</p>
	<table class="exception-table">
	<tr>
	<td>#UD</td>
	<td>If VEX.W = 1</td></tr></table></body></html>