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| <title>VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD — Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values </title></head> |
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| <h1>VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD — Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 -bit Mode</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>VEX.DDS.128.66.0F38.W1 97 /r</p> |
| <p>VFMSUBADD132PD <em>xmm0, xmm1, xmm2/m128</em></p></td> |
| <td>A</td> |
| <td>V/V</td> |
| <td>FMA</td> |
| <td>Multiply packed double-precision floating-point values from <em>xmm0</em> and <em>xmm2/mem</em>, subtract/add elements in <em>xmm1</em> and put result in <em>xmm0</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.DDS.128.66.0F38.W1 A7 /r</p> |
| <p>VFMSUBADD213PD<em> xmm0, xmm1, xmm2/m128</em></p></td> |
| <td>A</td> |
| <td>V/V</td> |
| <td>FMA</td> |
| <td>Multiply packed double-precision floating-point values from <em>xmm0</em> and <em>xmm1</em>, subtract/add ele-ments in <em>xmm2/mem</em> and put result in <em>xmm0</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.DDS.128.66.0F38.W1 B7 /r</p> |
| <p>VFMSUBADD231PD <em>xmm0, xmm1, xmm2/m128</em></p></td> |
| <td>A</td> |
| <td>V/V</td> |
| <td>FMA</td> |
| <td>Multiply packed double-precision floating-point values from <em>xmm1</em> and <em>xmm2/mem</em>, subtract/add elements in <em>xmm0</em> and put result in <em>xmm0</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.DDS.256.66.0F38.W1 97 /r</p> |
| <p>VFMSUBADD132PD <em>ymm0, ymm1, ymm2/m256</em></p></td> |
| <td>A</td> |
| <td>V/V</td> |
| <td>FMA</td> |
| <td>Multiply packed double-precision floating-point values from <em>ymm0</em> and <em>ymm2/mem</em>, subtract/add elements in <em>ymm1</em> and put result in <em>ymm0</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.DDS.256.66.0F38.W1 A7 /r</p> |
| <p>VFMSUBADD213PD <em>ymm0, ymm1, ymm2/m256</em></p></td> |
| <td>A</td> |
| <td>V/V</td> |
| <td>FMA</td> |
| <td>Multiply packed double-precision floating-point values from <em>ymm0</em> and <em>ymm1</em>, subtract/add ele-ments in <em>ymm2/mem</em> and put result in <em>ymm0</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.DDS.256.66.0F38.W1 B7 /r</p> |
| <p>VFMSUBADD231PD <em>ymm0, ymm1, ymm2/m256</em></p></td> |
| <td>A</td> |
| <td>V/V</td> |
| <td>FMA</td> |
| <td>Multiply packed double-precision floating-point values from <em>ymm1</em> and <em>ymm2/mem</em>, subtract/add elements in <em>ymm0</em> and put result in <em>ymm0</em>.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>A</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>VFMSUBADD132PD: Multiplies the two or four packed double-precision floating-point values from the first source operand to the two or four packed double-precision floating-point values in the third source operand. From the infi-nite precision intermediate result, subtracts the odd double-precision floating-point elements and adds the even double-precision floating-point values in the second source operand, performs rounding and stores the resulting two or four packed double-precision floating-point values to the destination operand (first source operand).</p> |
| <p>VFMSUBADD213PD: Multiplies the two or four packed double-precision floating-point values from the second source operand to the two or four packed double-precision floating-point values in the first source operand. From the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and adds the even double-precision floating-point values in the third source operand, performs rounding and stores the resulting two or four packed double-precision floating-point values to the destination operand (first source operand).</p> |
| <p>VFMSUBADD231PD: Multiplies the two or four packed double-precision floating-point values from the second source operand to the two or four packed double-precision floating-point values in the third source operand. From the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and adds the even double-precision floating-point values in the first source operand, performs rounding and stores the resulting two or four packed double-precision floating-point values to the destination operand (first source operand).</p> |
| <p>VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.</p> |
| <p>VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.</p> |
| <p>Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column. See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1</em>.</p> |
| <h2>Operation</h2> |
| <p>In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations with infinite precision inputs and outputs (no rounding).</p> |
| <p><strong>VFMSUBADD132PD DEST, SRC2, SRC3</strong></p> |
| <pre>IF (VEX.128) THEN |
| DEST[63:0] ← RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0]) |
| DEST[127:64] ← RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64]) |
| DEST[VLMAX-1:128] ← 0 |
| ELSEIF (VEX.256) |
| DEST[63:0] ← RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0]) |
| DEST[127:64] ← RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64]) |
| DEST[191:128] ← RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] + SRC2[191:128]) |
| DEST[255:192] ← RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] - SRC2[255:192] |
| FI</pre> |
| <p><strong>VFMSUBADD213PD DEST, SRC2, SRC3</strong></p> |
| <pre>IF (VEX.128) THEN |
| DEST[63:0] ← RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0]) |
| DEST[127:64] ← RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64]) |
| DEST[VLMAX-1:128] ← 0 |
| ELSEIF (VEX.256) |
| DEST[63:0] ← RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0]) |
| DEST[127:64] ← RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64]) |
| DEST[191:128] ← RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] + SRC3[191:128]) |
| DEST[255:192] ← RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] - SRC3[255:192] |
| FI</pre> |
| <p><strong>VFMSUBADD231PD DEST, SRC2, SRC3</strong></p> |
| <pre>IF (VEX.128) THEN |
| DEST[63:0] ← RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0]) |
| DEST[127:64] ← RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64]) |
| DEST[VLMAX-1:128] ← 0 |
| ELSEIF (VEX.256) |
| DEST[63:0] ← RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0]) |
| DEST[127:64] ← RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64]) |
| DEST[191:128] ← RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] + DEST[191:128]) |
| DEST[255:192] ← RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] - DEST[255:192] |
| FI</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>VFMSUBADD132PD: __m128d _mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c);</p> |
| <p>VFMSUBADD213PD: __m128d _mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c);</p> |
| <p>VFMSUBADD231PD: __m128d _mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c);</p> |
| <p>VFMSUBADD132PD: __m256d _mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c);</p> |
| <p>VFMSUBADD213PD: __m256d _mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c);</p> |
| <p>VFMSUBADD231PD: __m256d _mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c);</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>Overflow, Underflow, Invalid, Precision, Denormal</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 2</p></body></html> |