views/asm-docs-source/UNPCKLPS.html - compiler-explorer - Rivoreo Source Code Repositories

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 <h1>UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values</h1>
 <table>
 <tr>
 <th>Opcode/Instruction</th>
 <th>Op/En</th>
 <th>64/32 bit Mode Support</th>
 <th>CPUID Feature Flag</th>
 <th>Description</th></tr>
 <tr>
 <td>
 <p>0F 14 /<em>r</em></p>
 <p>UNPCKLPS <em>xmm1, xmm2/m128</em></p></td>
 <td>RM</td>
 <td>V/V</td>
 <td>SSE</td>
 <td>Unpacks and Interleaves single-precision floating-point values from low quadwords of <em>xmm1</em> and <em>xmm2/mem</em> into<em> xmm1</em>.</td></tr>
 <tr>
 <td>
 <p>VEX.NDS.128.0F.WIG 14 /r</p>
 <p>VUNPCKLPS <em>xmm1,xmm2, xmm3/m128</em></p></td>
 <td>RVM</td>
 <td>V/V</td>
 <td>AVX</td>
 <td>Unpacks and Interleaves single-precision floating-point values from low quadwords of <em>xmm2</em> and <em>xmm3/m128</em>.</td></tr>
 <tr>
 <td>
 <p>VEX.NDS.256.0F.WIG 14 /r</p>
 <p>VUNPCKLPS <em>ymm1,ymm2,ymm3/m256</em></p></td>
 <td>RVM</td>
 <td>V/V</td>
 <td>AVX</td>
 <td>Unpacks and Interleaves single-precision floating-point values from low quadwords of <em>ymm2</em> and <em>ymm3/m256</em>.</td></tr></table>
 <h3>Instruction Operand Encoding</h3>
 <table>
 <tr>
 <td>Op/En</td>
 <td>Operand 1</td>
 <td>Operand 2</td>
 <td>Operand 3</td>
 <td>Operand 4</td></tr>
 <tr>
 <td>RM</td>
 <td>ModRM:reg (r, w)</td>
 <td>ModRM:r/m (r)</td>
 <td>NA</td>
 <td>NA</td></tr>
 <tr>
 <td>RVM</td>
 <td>ModRM:reg (w)</td>
 <td>VEX.vvvv (r)</td>
 <td>ModRM:r/m (r)</td>
 <td>NA</td></tr></table>
 <h2>Description</h2>
 <p>Performs an interleaved unpack of the low-order single-precision floating-point values from the source operand (second operand) and the destination operand (first operand). See Figure 4-26. The source operand can be an XMM register or a 128-bit memory location; the destination operand is an XMM register.</p>
 <svg width="568.799985" viewBox="111.840000 803476.019995 379.199990 156.360005" height="234.5400075">
 <text y="803508.887484" x="144.06" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="21.320964">DEST</text>
 <text y="803554.907384" x="148.5001" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="16.860144">SRC</text>
 <text y="803616.707684" x="144.06" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="21.320964">DEST</text>
 <rect y="803497.44" x="242.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <rect y="803542.44" x="242.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <rect y="803497.44" x="170.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <rect y="803497.44" x="314.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <rect y="803497.44" x="386.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <rect y="803542.44" x="170.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <rect y="803542.44" x="314.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <rect y="803542.44" x="386.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <rect y="803605.44" x="169.62" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <rect y="803605.44" x="241.62" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <rect y="803605.44" x="313.62" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
 <path style="stroke:black" d="M170.040000,803542.200000 L170.040000,803560.440000 L170.520000,803560.440000 L170.520000,803542.200000 "></path>
 <path style="stroke:black" d="M242.040000,803542.200000 L242.040000,803560.440000 L242.520010,803560.440000 L242.520010,803542.200000 "></path>
 <path style="stroke:black" d="M314.040000,803542.200000 L314.040000,803560.440000 L314.519980,803560.440000 L314.519980,803542.200000 "></path>
 <path style="stroke:black" d="M386.040000,803542.200000 L386.040000,803560.440000 L386.519980,803560.440000 L386.519980,803542.200000 "></path>
 <path style="stroke:black" d="M170.280000,803542.200020 L170.280000,803542.680000 L242.520000,803542.680000 L242.520000,803542.200020 "></path>
 <path style="stroke:black" d="M242.280000,803542.200020 L242.280000,803542.680000 L314.520000,803542.680000 L314.520000,803542.200020 "></path>
 <path style="stroke:black" d="M314.280000,803542.200020 L314.280000,803542.680000 L386.520000,803542.680000 L386.520000,803542.200020 "></path>
 <path style="stroke:black" d="M386.280000,803542.200020 L386.280000,803542.680000 L458.520000,803542.680000 L458.520000,803542.200020 "></path>
 <path style="stroke:black" d="M242.040000,803542.440000 L242.040000,803560.680000 L242.520010,803560.680000 L242.520010,803542.440000 "></path>
 <path style="stroke:black" d="M314.040000,803542.440000 L314.040000,803560.680000 L314.519980,803560.680000 L314.519980,803542.440000 "></path>
 <path style="stroke:black" d="M386.040000,803542.440000 L386.040000,803560.680000 L386.519980,803560.680000 L386.519980,803542.440000 "></path>
 <path style="stroke:black" d="M458.040000,803542.440000 L458.040000,803560.680000 L458.519980,803560.680000 L458.519980,803542.440000 "></path>
 <path style="stroke:black" d="M170.040000,803560.199990 L170.040000,803560.680000 L242.280000,803560.680000 L242.280000,803560.199990 "></path>
 <path style="stroke:black" d="M242.040000,803560.199990 L242.040000,803560.680000 L314.280000,803560.680000 L314.280000,803560.199990 "></path>
 <path style="stroke:black" d="M314.040000,803560.199990 L314.040000,803560.680000 L386.280000,803560.680000 L386.280000,803560.199990 "></path>
 <path style="stroke:black" d="M386.040000,803560.199990 L386.040000,803560.680000 L458.280000,803560.680000 L458.280000,803560.199990 "></path>
 <text y="803508.887484" x="273.543012" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.713256">X2</text>
 <text y="803553.887484" x="274.500612" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y2</text>
 <text y="803508.887484" x="204.84" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">X3</text>
 <text y="803508.887484" x="345.541764" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.713256">X1</text>
 <text y="803508.887484" x="417.540516" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">X0</text>
 <text y="803553.887484" x="204.84" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y3</text>
 <text y="803553.887484" x="339.836064" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y1</text>
 <text y="803553.887484" x="411.834816" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y0</text>
 <text y="803616.77786" x="204.0" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y1</text>
 <text y="803616.77786" x="276.238152" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">X1</text>
 <text y="803616.77786" x="348.236904" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y0</text></svg>
 <h3>Figure 4-26.  UNPCKLPS Instruction Low Unpack and Interleave Operation</h3>
 <p>When unpacking from a memory operand, an implementation may fetch only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be enforced.</p>
 <p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
 <p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.</p>
 <p>VEX.128 encoded version: The first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.</p>
 <h2>Operation</h2>
 <p><strong>UNPCKLPS (128-bit Legacy SSE version)</strong></p>
 <pre>DEST[31:0] ← SRC1[31:0]
 DEST[63:32] ← SRC2[31:0]
 DEST[95:64] ← SRC1[63:32]
 DEST[127:96] ← SRC2[63:32]
 DEST[VLMAX-1:128] (Unmodified)</pre>
 <p><strong>VUNPCKLPS (VEX.128 encoded version)</strong></p>
 <pre>DEST[31:0] ← SRC1[31:0]
 DEST[63:32] ← SRC2[31:0]
 DEST[95:64] ← SRC1[63:32]
 DEST[127:96] ← SRC2[63:32]
 DEST[VLMAX-1:128] ← 0
 UNPCKLPS (VEX.256 encoded version)
 DEST[31:0] ← SRC1[31:0]
 DEST[63:32] ← SRC2[31:0]
 DEST[95:64] ← SRC1[63:32]
 DEST[127:96] ← SRC2[63:32]
 DEST[159:128] ← SRC1[159:128]
 DEST[191:160] ← SRC2[159:128]
 DEST[223:192] ← SRC1[191:160]
 DEST[255:224] ← SRC2[191:160]</pre>
 <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
 <p>UNPCKLPS:</p>
 <p>__m128 _mm_unpacklo_ps(__m128 a, __m128 b)</p>
 <p>UNPCKLPS:</p>
 <p>__m256 _mm256_unpacklo_ps (__m256 a, __m256 b);</p>
 <h2>SIMD Floating-Point Exceptions</h2>
 <p>None.</p>
 <h2>Other Exceptions</h2>
 <p>See Exceptions Type 4.</p></body></html>
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	<html>
	<head>
	<meta charset="UTF-8">
	<link href="style.css" type="text/css" rel="stylesheet">
	<title>UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values </title></head>
	<body>
	<h1>UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values</h1>
	<table>
	<tr>
	<th>Opcode/Instruction</th>
	<th>Op/En</th>
	<th>64/32 bit Mode Support</th>
	<th>CPUID Feature Flag</th>
	<th>Description</th></tr>
	<tr>
	<td>
	<p>0F 14 /<em>r</em></p>
	<p>UNPCKLPS <em>xmm1, xmm2/m128</em></p></td>
	<td>RM</td>
	<td>V/V</td>
	<td>SSE</td>
	<td>Unpacks and Interleaves single-precision floating-point values from low quadwords of <em>xmm1</em> and <em>xmm2/mem</em> into<em> xmm1</em>.</td></tr>
	<tr>
	<td>
	<p>VEX.NDS.128.0F.WIG 14 /r</p>
	<p>VUNPCKLPS <em>xmm1,xmm2, xmm3/m128</em></p></td>
	<td>RVM</td>
	<td>V/V</td>
	<td>AVX</td>
	<td>Unpacks and Interleaves single-precision floating-point values from low quadwords of <em>xmm2</em> and <em>xmm3/m128</em>.</td></tr>
	<tr>
	<td>
	<p>VEX.NDS.256.0F.WIG 14 /r</p>
	<p>VUNPCKLPS <em>ymm1,ymm2,ymm3/m256</em></p></td>
	<td>RVM</td>
	<td>V/V</td>
	<td>AVX</td>
	<td>Unpacks and Interleaves single-precision floating-point values from low quadwords of <em>ymm2</em> and <em>ymm3/m256</em>.</td></tr></table>
	<h3>Instruction Operand Encoding</h3>
	<table>
	<tr>
	<td>Op/En</td>
	<td>Operand 1</td>
	<td>Operand 2</td>
	<td>Operand 3</td>
	<td>Operand 4</td></tr>
	<tr>
	<td>RM</td>
	<td>ModRM:reg (r, w)</td>
	<td>ModRM:r/m (r)</td>
	<td>NA</td>
	<td>NA</td></tr>
	<tr>
	<td>RVM</td>
	<td>ModRM:reg (w)</td>
	<td>VEX.vvvv (r)</td>
	<td>ModRM:r/m (r)</td>
	<td>NA</td></tr></table>
	<h2>Description</h2>
	<p>Performs an interleaved unpack of the low-order single-precision floating-point values from the source operand (second operand) and the destination operand (first operand). See Figure 4-26. The source operand can be an XMM register or a 128-bit memory location; the destination operand is an XMM register.</p>
	<svg width="568.799985" viewBox="111.840000 803476.019995 379.199990 156.360005" height="234.5400075">
	<text y="803508.887484" x="144.06" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="21.320964">DEST</text>
	<text y="803554.907384" x="148.5001" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="16.860144">SRC</text>
	<text y="803616.707684" x="144.06" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="21.320964">DEST</text>
	<rect y="803497.44" x="242.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<rect y="803542.44" x="242.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<rect y="803497.44" x="170.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<rect y="803497.44" x="314.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<rect y="803497.44" x="386.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<rect y="803542.44" x="170.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<rect y="803542.44" x="314.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<rect y="803542.44" x="386.28" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<rect y="803605.44" x="169.62" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<rect y="803605.44" x="241.62" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<rect y="803605.44" x="313.62" style="fill:rgba(0,0,0,0);stroke:rgb(0,0,0);stroke-width:1pt;" height="18.0" width="72.0"></rect>
	<path style="stroke:black" d="M170.040000,803542.200000 L170.040000,803560.440000 L170.520000,803560.440000 L170.520000,803542.200000 "></path>
	<path style="stroke:black" d="M242.040000,803542.200000 L242.040000,803560.440000 L242.520010,803560.440000 L242.520010,803542.200000 "></path>
	<path style="stroke:black" d="M314.040000,803542.200000 L314.040000,803560.440000 L314.519980,803560.440000 L314.519980,803542.200000 "></path>
	<path style="stroke:black" d="M386.040000,803542.200000 L386.040000,803560.440000 L386.519980,803560.440000 L386.519980,803542.200000 "></path>
	<path style="stroke:black" d="M170.280000,803542.200020 L170.280000,803542.680000 L242.520000,803542.680000 L242.520000,803542.200020 "></path>
	<path style="stroke:black" d="M242.280000,803542.200020 L242.280000,803542.680000 L314.520000,803542.680000 L314.520000,803542.200020 "></path>
	<path style="stroke:black" d="M314.280000,803542.200020 L314.280000,803542.680000 L386.520000,803542.680000 L386.520000,803542.200020 "></path>
	<path style="stroke:black" d="M386.280000,803542.200020 L386.280000,803542.680000 L458.520000,803542.680000 L458.520000,803542.200020 "></path>
	<path style="stroke:black" d="M242.040000,803542.440000 L242.040000,803560.680000 L242.520010,803560.680000 L242.520010,803542.440000 "></path>
	<path style="stroke:black" d="M314.040000,803542.440000 L314.040000,803560.680000 L314.519980,803560.680000 L314.519980,803542.440000 "></path>
	<path style="stroke:black" d="M386.040000,803542.440000 L386.040000,803560.680000 L386.519980,803560.680000 L386.519980,803542.440000 "></path>
	<path style="stroke:black" d="M458.040000,803542.440000 L458.040000,803560.680000 L458.519980,803560.680000 L458.519980,803542.440000 "></path>
	<path style="stroke:black" d="M170.040000,803560.199990 L170.040000,803560.680000 L242.280000,803560.680000 L242.280000,803560.199990 "></path>
	<path style="stroke:black" d="M242.040000,803560.199990 L242.040000,803560.680000 L314.280000,803560.680000 L314.280000,803560.199990 "></path>
	<path style="stroke:black" d="M314.040000,803560.199990 L314.040000,803560.680000 L386.280000,803560.680000 L386.280000,803560.199990 "></path>
	<path style="stroke:black" d="M386.040000,803560.199990 L386.040000,803560.680000 L458.280000,803560.680000 L458.280000,803560.199990 "></path>
	<text y="803508.887484" x="273.543012" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.713256">X2</text>
	<text y="803553.887484" x="274.500612" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y2</text>
	<text y="803508.887484" x="204.84" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">X3</text>
	<text y="803508.887484" x="345.541764" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.713256">X1</text>
	<text y="803508.887484" x="417.540516" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">X0</text>
	<text y="803553.887484" x="204.84" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y3</text>
	<text y="803553.887484" x="339.836064" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y1</text>
	<text y="803553.887484" x="411.834816" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y0</text>
	<text y="803616.77786" x="204.0" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y1</text>
	<text y="803616.77786" x="276.238152" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">X1</text>
	<text y="803616.77786" x="348.236904" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">Y0</text></svg>
	<h3>Figure 4-26. UNPCKLPS Instruction Low Unpack and Interleave Operation</h3>
	<p>When unpacking from a memory operand, an implementation may fetch only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be enforced.</p>
	<p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
	<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.</p>
	<p>VEX.128 encoded version: The first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.</p>
	<h2>Operation</h2>
	<p><strong>UNPCKLPS (128-bit Legacy SSE version)</strong></p>
	<pre>DEST[31:0] ← SRC1[31:0]
	DEST[63:32] ← SRC2[31:0]
	DEST[95:64] ← SRC1[63:32]
	DEST[127:96] ← SRC2[63:32]
	DEST[VLMAX-1:128] (Unmodified)</pre>
	<p><strong>VUNPCKLPS (VEX.128 encoded version)</strong></p>
	<pre>DEST[31:0] ← SRC1[31:0]
	DEST[63:32] ← SRC2[31:0]
	DEST[95:64] ← SRC1[63:32]
	DEST[127:96] ← SRC2[63:32]
	DEST[VLMAX-1:128] ← 0
	UNPCKLPS (VEX.256 encoded version)
	DEST[31:0] ← SRC1[31:0]
	DEST[63:32] ← SRC2[31:0]
	DEST[95:64] ← SRC1[63:32]
	DEST[127:96] ← SRC2[63:32]
	DEST[159:128] ← SRC1[159:128]
	DEST[191:160] ← SRC2[159:128]
	DEST[223:192] ← SRC1[191:160]
	DEST[255:224] ← SRC2[191:160]</pre>
	<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
	<p>UNPCKLPS:</p>
	<p>__m128 _mm_unpacklo_ps(__m128 a, __m128 b)</p>
	<p>UNPCKLPS:</p>
	<p>__m256 _mm256_unpacklo_ps (__m256 a, __m256 b);</p>
	<h2>SIMD Floating-Point Exceptions</h2>
	<p>None.</p>
	<h2>Other Exceptions</h2>
	<p>See Exceptions Type 4.</p></body></html>