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| <title>UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values </title></head> |
| <body> |
| <h1>UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 bit Mode Support</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>0F 15 /<em>r</em></p> |
| <p>UNPCKHPS <em>xmm1, xmm2/m128</em></p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE</td> |
| <td>Unpacks and Interleaves single-precision floating-point values from high quadwords of <em>xmm1</em> and <em>xmm2/mem</em> into <em>xmm1</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.NDS.128.0F.WIG 15 /r</p> |
| <p>VUNPCKHPS <em>xmm1,xmm2, xmm3/m128</em></p></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Unpacks and Interleaves single-precision floating-point values from high quadwords of <em>xmm2</em> and <em>xmm3/m128</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.NDS.256.0F.WIG 15 /r</p> |
| <p>VUNPCKHPS <em>ymm1,ymm2,ymm3/m256</em></p></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Unpacks and Interleaves single-precision floating-point values from high quadwords of <em>ymm2</em> and <em>ymm3/m256</em>.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RVM</td> |
| <td>ModRM:reg (w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Performs an interleaved unpack of the high-order single-precision floating-point values from the source operand (second operand) and the destination operand (first operand). See Figure 4-24. The source operand can be an XMM register or a 128-bit memory location; the destination operand is an XMM register.</p> |
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| <h3>Figure 4-24. UNPCKHPS Instruction High Unpack and Interleave Operation</h3> |
| <p>When unpacking from a memory operand, an implementation may fetch only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be enforced.</p> |
| <p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p> |
| <p>128-bit Legacy SSE version: T second source can be an XMM register or an 128-bit memory location. The destina-tion is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.</p> |
| <p>VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.</p> |
| <h2>Operation</h2> |
| <p><strong>UNPCKHPS (128-bit Legacy SSE version)</strong></p> |
| <pre>DEST[31:0] ← SRC1[95:64] |
| DEST[63:32] ← SRC2[95:64] |
| DEST[95:64] ← SRC1[127:96] |
| DEST[127:96] ← SRC2[127:96] |
| DEST[VLMAX-1:128] (Unmodified)</pre> |
| <p><strong>VUNPCKHPS (VEX.128 encoded version)</strong></p> |
| <pre>DEST[31:0] ← SRC1[95:64] |
| DEST[63:32] ← SRC2[95:64] |
| DEST[95:64] ← SRC1[127:96] |
| DEST[127:96] ← SRC2[127:96] |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VUNPCKHPS (VEX.256 encoded version)</strong></p> |
| <pre>DEST[31:0] ← SRC1[95:64] |
| DEST[63:32] ← SRC2[95:64] |
| DEST[95:64] ← SRC1[127:96] |
| DEST[127:96] ← SRC2[127:96] |
| DEST[159:128] ← SRC1[223:192] |
| DEST[191:160] ← SRC2[223:192] |
| DEST[223:192] ← SRC1[255:224] |
| DEST[255:224] ← SRC2[255:224]</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>UNPCKHPS:</p> |
| <p>__m128 _mm_unpackhi_ps(__m128 a, __m128 b)</p> |
| <p>UNPCKHPS:</p> |
| <p>__m256 _mm256_unpackhi_ps (__m256 a, __m256 b);</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>None.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 4.</p></body></html> |