views/asm-docs-source/TZCNT.html - compiler-explorer - Rivoreo Source Code Repositories

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 <title>TZCNT — Count the Number of Trailing Zero Bits </title></head>
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 <h1>TZCNT — Count the Number of Trailing Zero Bits</h1>
 <table>
 <tr>
 <th>Opcode/Instruction</th>
 <th>Op/En</th>
 <th>64/32 -bit Mode</th>
 <th>CPUID Feature Flag</th>
 <th>Description</th></tr>
 <tr>
 <td>
 <p>F3 0F BC /r</p>
 <p>TZCNT <em>r16, r/m16</em></p></td>
 <td>RM</td>
 <td>V/V</td>
 <td>BMI1</td>
 <td>Count the number of trailing zero bits in<em> r/m16</em>, return result in <em>r16</em>.</td></tr>
 <tr>
 <td>
 <p>F3 0F BC /r</p>
 <p>TZCNT<em> r32, r/m32</em></p></td>
 <td>RM</td>
 <td>V/V</td>
 <td>BMI1</td>
 <td>Count the number of trailing zero bits in <em>r/m32</em>, return result in <em>r32.</em></td></tr>
 <tr>
 <td>
 <p>REX.W + F3 0F BC /r</p>
 <p>TZCNT <em>r64, r/m64</em></p></td>
 <td>RM</td>
 <td>V/N.E.</td>
 <td>BMI1</td>
 <td>Count the number of trailing zero bits in<em> r/m64</em>, return result in <em>r64</em>.</td></tr></table>
 <h3>Instruction Operand Encoding</h3>
 <table>
 <tr>
 <td>Op/En</td>
 <td>Operand 1</td>
 <td>Operand 2</td>
 <td>Operand 3</td>
 <td>Operand 4</td></tr>
 <tr>
 <td>A</td>
 <td>ModRM:reg (w)</td>
 <td>ModRM:r/m (r)</td>
 <td>NA</td>
 <td>NA</td></tr></table>
 <h2>Description</h2>
 <p>TZCNT counts the number of trailing least significant zero bits in source operand (second operand) and returns the result in destination operand (first operand). TZCNT is an extension of the BSF instruction. The key difference between TZCNT and BSF instruction is that TZCNT provides operand size as output when source operand is zero while in the case of BSF instruction, if source operand is zero, the content of destination operand are undefined. On processors that do not support TZCNT, the instruction byte encoding is executed as BSF.</p>
 <h2>Operation</h2>
 <pre>temp ← 0
 DEST ← 0
 DO WHILE ( (temp &lt; OperandSize) and (SRC[ temp] = 0) )
     temp ← temp +1
     DEST ← DEST+ 1
 OD
 IF DEST = OperandSize
     CF ← 1
 ELSE
     CF ← 0
 FI
 IF DEST = 0
     ZF ← 1
 ELSE
     ZF ← 0
 FI</pre>
 <h2>Flags Affected</h2>
 <p>ZF is set to 1 in case of zero output (least significant bit of the source is set), and to 0 otherwise, CF is set to 1 if the input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.</p>
 <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
 <p>TZCNT:</p>
 <p>unsigned __int32 _tzcnt_u32(unsigned __int32 src);</p>
 <p>TZCNT:</p>
 <p>unsigned __int64 _tzcnt_u64(unsigned __int64 src);</p>
 <h2>Protected Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP(0)</td>
 <td>
 <p>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</p>
 <p>If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</p></td></tr>
 <tr>
 <td>#SS(0)</td>
 <td>For an illegal address in the SS segment.</td></tr>
 <tr>
 <td>#PF (fault-code)</td>
 <td>For a page fault.</td></tr>
 <tr>
 <td>#AC(0)</td>
 <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table>
 <h2>Real-Address Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP(0)</td>
 <td>If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.</td></tr>
 <tr>
 <td>#SS(0)</td>
 <td>For an illegal address in the SS segment.</td></tr></table>
 <h2>Virtual 8086 Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP(0)</td>
 <td>If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.</td></tr>
 <tr>
 <td>#SS(0)</td>
 <td>For an illegal address in the SS segment.</td></tr>
 <tr>
 <td>#PF (fault-code)</td>
 <td>For a page fault.</td></tr>
 <tr>
 <td>#AC(0)</td>
 <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table>
 <h2>Compatibility Mode Exceptions</h2>
 <p>Same exceptions as in Protected Mode.</p>
 <h2>64-Bit Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP(0)</td>
 <td>If the memory address is in a non-canonical form.</td></tr>
 <tr>
 <td>#SS(0)</td>
 <td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
 <tr>
 <td>#PF (fault-code)</td>
 <td>For a page fault.</td></tr>
 <tr>
 <td>#AC(0)</td>
 <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table></body></html>
	<!DOCTYPE html>

	<html>
	<head>
	<meta charset="UTF-8">
	<link href="style.css" type="text/css" rel="stylesheet">
	<title>TZCNT — Count the Number of Trailing Zero Bits </title></head>
	<body>
	<h1>TZCNT — Count the Number of Trailing Zero Bits</h1>
	<table>
	<tr>
	<th>Opcode/Instruction</th>
	<th>Op/En</th>
	<th>64/32 -bit Mode</th>
	<th>CPUID Feature Flag</th>
	<th>Description</th></tr>
	<tr>
	<td>
	<p>F3 0F BC /r</p>
	<p>TZCNT <em>r16, r/m16</em></p></td>
	<td>RM</td>
	<td>V/V</td>
	<td>BMI1</td>
	<td>Count the number of trailing zero bits in<em> r/m16</em>, return result in <em>r16</em>.</td></tr>
	<tr>
	<td>
	<p>F3 0F BC /r</p>
	<p>TZCNT<em> r32, r/m32</em></p></td>
	<td>RM</td>
	<td>V/V</td>
	<td>BMI1</td>
	<td>Count the number of trailing zero bits in <em>r/m32</em>, return result in <em>r32.</em></td></tr>
	<tr>
	<td>
	<p>REX.W + F3 0F BC /r</p>
	<p>TZCNT <em>r64, r/m64</em></p></td>
	<td>RM</td>
	<td>V/N.E.</td>
	<td>BMI1</td>
	<td>Count the number of trailing zero bits in<em> r/m64</em>, return result in <em>r64</em>.</td></tr></table>
	<h3>Instruction Operand Encoding</h3>
	<table>
	<tr>
	<td>Op/En</td>
	<td>Operand 1</td>
	<td>Operand 2</td>
	<td>Operand 3</td>
	<td>Operand 4</td></tr>
	<tr>
	<td>A</td>
	<td>ModRM:reg (w)</td>
	<td>ModRM:r/m (r)</td>
	<td>NA</td>
	<td>NA</td></tr></table>
	<h2>Description</h2>
	<p>TZCNT counts the number of trailing least significant zero bits in source operand (second operand) and returns the result in destination operand (first operand). TZCNT is an extension of the BSF instruction. The key difference between TZCNT and BSF instruction is that TZCNT provides operand size as output when source operand is zero while in the case of BSF instruction, if source operand is zero, the content of destination operand are undefined. On processors that do not support TZCNT, the instruction byte encoding is executed as BSF.</p>
	<h2>Operation</h2>
	<pre>temp ← 0
	DEST ← 0
	DO WHILE ( (temp < OperandSize) and (SRC[ temp] = 0) )
	temp ← temp +1
	DEST ← DEST+ 1
	OD
	IF DEST = OperandSize
	CF ← 1
	ELSE
	CF ← 0
	FI
	IF DEST = 0
	ZF ← 1
	ELSE
	ZF ← 0
	FI</pre>
	<h2>Flags Affected</h2>
	<p>ZF is set to 1 in case of zero output (least significant bit of the source is set), and to 0 otherwise, CF is set to 1 if the input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.</p>
	<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
	<p>TZCNT:</p>
	<p>unsigned __int32 _tzcnt_u32(unsigned __int32 src);</p>
	<p>TZCNT:</p>
	<p>unsigned __int64 _tzcnt_u64(unsigned __int64 src);</p>
	<h2>Protected Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP(0)</td>
	<td>
	<p>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</p>
	<p>If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</p></td></tr>
	<tr>
	<td>#SS(0)</td>
	<td>For an illegal address in the SS segment.</td></tr>
	<tr>
	<td>#PF (fault-code)</td>
	<td>For a page fault.</td></tr>
	<tr>
	<td>#AC(0)</td>
	<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table>
	<h2>Real-Address Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP(0)</td>
	<td>If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.</td></tr>
	<tr>
	<td>#SS(0)</td>
	<td>For an illegal address in the SS segment.</td></tr></table>
	<h2>Virtual 8086 Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP(0)</td>
	<td>If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.</td></tr>
	<tr>
	<td>#SS(0)</td>
	<td>For an illegal address in the SS segment.</td></tr>
	<tr>
	<td>#PF (fault-code)</td>
	<td>For a page fault.</td></tr>
	<tr>
	<td>#AC(0)</td>
	<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table>
	<h2>Compatibility Mode Exceptions</h2>
	<p>Same exceptions as in Protected Mode.</p>
	<h2>64-Bit Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP(0)</td>
	<td>If the memory address is in a non-canonical form.</td></tr>
	<tr>
	<td>#SS(0)</td>
	<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
	<tr>
	<td>#PF (fault-code)</td>
	<td>For a page fault.</td></tr>
	<tr>
	<td>#AC(0)</td>
	<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table></body></html>