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| <title>SUBPD—Subtract Packed Double-Precision Floating-Point Values </title></head> |
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| <h1>SUBPD—Subtract Packed Double-Precision Floating-Point Values</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 bit Mode Support</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>66 0F 5C /<em>r</em></p> |
| <p>SUBPD <em>xmm1, xmm2/m128</em></p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE2</td> |
| <td>Subtract packed double-precision floating-point values in <em>xmm2/m128</em> from <em>xmm1</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.NDS.128.66.0F.WIG 5C /r</p> |
| <p>VSUBPD <em>xmm1,xmm2, xmm3/m128</em></p></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Subtract packed double-precision floating-point values in <em>xmm3/mem</em> from <em>xmm2</em> and stores result in <em>xmm1</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.NDS.256.66.0F.WIG 5C /r</p> |
| <p>VSUBPD <em>ymm1, ymm2, ymm3/m256</em></p></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Subtract packed double-precision floating-point values in <em>ymm3/mem</em> from <em>ymm2 </em>and stores result in <em>ymm1</em>.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RVM</td> |
| <td>ModRM:reg (w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Performs a SIMD subtract of the two packed double-precision floating-point values in the source operand (second operand) from the two packed double-precision floating-point values in the destination operand (first operand), and stores the packed double-precision floating-point results in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See Figure 11-3 in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1</em>, for an illustration of a SIMD double-precision floating-point operation.</p> |
| <p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p> |
| <p>128-bit Legacy SSE version: T second source can be an XMM register or an 128-bit memory location. The destina-tion is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.</p> |
| <p>VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.</p> |
| <p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p> |
| <h2>Operation</h2> |
| <p><strong>SUBPD (128-bit Legacy SSE version)</strong></p> |
| <pre>DEST[63:0] ← DEST[63:0] - SRC[63:0] |
| DEST[127:64] ← DEST[127:64] - SRC[127:64] |
| DEST[VLMAX-1:128] (Unmodified)</pre> |
| <p><strong>VSUBPD (VEX.128 encoded version)</strong></p> |
| <pre>DEST[63:0] ← SRC1[63:0] - SRC2[63:0] |
| DEST[127:64] ← SRC1[127:64] - SRC2[127:64] |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VSUBPD (VEX.256 encoded version)</strong></p> |
| <pre>DEST[63:0] ← SRC1[63:0] - SRC2[63:0] |
| DEST[127:64] ← SRC1[127:64] - SRC2[127:64] |
| DEST[191:128] ← SRC1[191:128] - SRC2[191:128] |
| DEST[255:192] ← SRC1[255:192] - SRC2[255:192]</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>SUBPD:</p> |
| <p>__m128d _mm_sub_pd (m128d a, m128d b)</p> |
| <p>VSUBPD:</p> |
| <p>__m256d _mm256_sub_pd (__m256d a, __m256d b);</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>Overflow, Underflow, Invalid, Precision, Denormal.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 2.</p></body></html> |