| <!DOCTYPE html> |
| |
| <html> |
| <head> |
| <meta charset="UTF-8"> |
| <link href="style.css" type="text/css" rel="stylesheet"> |
| <title>SUB—Subtract </title></head> |
| <body> |
| <h1>SUB—Subtract</h1> |
| <table> |
| <tr> |
| <th>Opcode</th> |
| <th>Instruction</th> |
| <th>Op/En</th> |
| <th>64-Bit Mode</th> |
| <th>Compat/Leg Mode</th> |
| <th>Description</th></tr> |
| <tr> |
| <td>2C <em>ib</em></td> |
| <td>SUB AL, i<em>mm8</em></td> |
| <td>I</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>imm8</em> from AL.</td></tr> |
| <tr> |
| <td>2D <em>iw</em></td> |
| <td>SUB AX, i<em>mm16</em></td> |
| <td>I</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>imm16</em> from AX.</td></tr> |
| <tr> |
| <td>2D <em>id</em></td> |
| <td>SUB EAX, i<em>mm32</em></td> |
| <td>I</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>imm32</em> from EAX.</td></tr> |
| <tr> |
| <td>REX.W + 2D <em>id</em></td> |
| <td>SUB RAX, i<em>mm32</em></td> |
| <td>I</td> |
| <td>Valid</td> |
| <td>N.E.</td> |
| <td>Subtract <em>imm32 </em>sign-extended to 64-bits from RAX.</td></tr> |
| <tr> |
| <td>80 /5 <em>ib</em></td> |
| <td>SUB <em>r/m8, imm8</em></td> |
| <td>MI</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>imm8</em> from <em>r/m8.</em></td></tr> |
| <tr> |
| <td>REX + 80 /5 <em>ib</em></td> |
| <td>SUB <em>r/m8*, imm8</em></td> |
| <td>MI</td> |
| <td>Valid</td> |
| <td>N.E.</td> |
| <td>Subtract <em>imm8</em> from <em>r/m8.</em></td></tr> |
| <tr> |
| <td>81 /5 <em>iw</em></td> |
| <td>SUB <em>r/m16, imm16</em></td> |
| <td>MI</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>imm16</em> from <em>r/m16.</em></td></tr> |
| <tr> |
| <td>81 /5 <em>id</em></td> |
| <td>SUB <em>r/m32, imm32</em></td> |
| <td>MI</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>imm32</em> from <em>r/m32.</em></td></tr> |
| <tr> |
| <td>REX.W + 81 /5 <em>id</em></td> |
| <td>SUB <em>r/m64, imm32</em></td> |
| <td>MI</td> |
| <td>Valid</td> |
| <td>N.E.</td> |
| <td>Subtract <em>imm32 </em>sign-extended to 64-bits from <em>r/m64.</em></td></tr> |
| <tr> |
| <td>83 /5 <em>ib</em></td> |
| <td>SUB <em>r/m16, imm8</em></td> |
| <td>MI</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract sign-extended <em>imm8</em> from <em>r/m16.</em></td></tr> |
| <tr> |
| <td>83 /5 <em>ib</em></td> |
| <td>SUB <em>r/m32, imm8</em></td> |
| <td>MI</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract sign-extended <em>imm8</em> from <em>r/m32.</em></td></tr> |
| <tr> |
| <td>REX.W + 83 /5 <em>ib</em></td> |
| <td>SUB <em>r/m64, imm8</em></td> |
| <td>MI</td> |
| <td>Valid</td> |
| <td>N.E.</td> |
| <td>Subtract sign-extended <em>imm8</em> from <em>r/m64.</em></td></tr> |
| <tr> |
| <td>28 /<em>r</em></td> |
| <td>SUB <em>r/m8, r8</em></td> |
| <td>MR</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>r8</em> from <em>r/m8.</em></td></tr> |
| <tr> |
| <td>REX + 28 /<em>r</em></td> |
| <td>SUB <em>r/m8*, r8*</em></td> |
| <td>MR</td> |
| <td>Valid</td> |
| <td>N.E.</td> |
| <td>Subtract <em>r8</em> from <em>r/m8.</em></td></tr> |
| <tr> |
| <td>29 /<em>r</em></td> |
| <td>SUB <em>r/m16, r16</em></td> |
| <td>MR</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>r16</em> from <em>r/m16.</em></td></tr> |
| <tr> |
| <td>29 /<em>r</em></td> |
| <td>SUB <em>r/m32, r32</em></td> |
| <td>MR</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>r32</em> from <em>r/m32.</em></td></tr> |
| <tr> |
| <td>REX.W + 29 /<em>r</em></td> |
| <td>SUB <em>r/m64, r64</em></td> |
| <td>MR</td> |
| <td>Valid</td> |
| <td>N.E.</td> |
| <td>Subtract <em>r64</em> from <em>r/m64.</em></td></tr> |
| <tr> |
| <td>2A /<em>r</em></td> |
| <td>SUB <em>r8, r/m8</em></td> |
| <td>RM</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>r/m8</em> from <em>r8.</em></td></tr> |
| <tr> |
| <td>REX + 2A /<em>r</em></td> |
| <td>SUB <em>r8*, r/m8*</em></td> |
| <td>RM</td> |
| <td>Valid</td> |
| <td>N.E.</td> |
| <td>Subtract <em>r/m8</em> from <em>r8.</em></td></tr> |
| <tr> |
| <td>2B /<em>r</em></td> |
| <td>SUB <em>r16, r/m16</em></td> |
| <td>RM</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>r/m16</em> from <em>r16.</em></td></tr> |
| <tr> |
| <td>2B /<em>r</em></td> |
| <td>SUB <em>r32, r/m32</em></td> |
| <td>RM</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Subtract <em>r/m32</em> from <em>r32.</em></td></tr> |
| <tr> |
| <td>REX.W + 2B /<em>r</em></td> |
| <td>SUB <em>r64, r/m64</em></td> |
| <td>RM</td> |
| <td>Valid</td> |
| <td>N.E.</td> |
| <td>Subtract <em>r/m64</em> from <em>r64.</em></td></tr></table> |
| <p><strong>NOTES:</strong></p> |
| <p>*</p> |
| <p>In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.</p> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>I</td> |
| <td>AL/AX/EAX/RAX</td> |
| <td>imm8/26/32</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>MI</td> |
| <td>ModRM:r/m (r, w)</td> |
| <td>imm8/26/32</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>MR</td> |
| <td>ModRM:r/m (r, w)</td> |
| <td>ModRM:reg (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, register, or memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.</p> |
| <p>The SUB instruction performs integer subtraction. It evaluates the result for both signed and unsigned integer operands and sets the OF and CF flags to indicate an overflow in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.</p> |
| <p>In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p> |
| <p>This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.</p> |
| <h2>Operation</h2> |
| <pre>DEST ← (DEST – SRC);</pre> |
| <h2>Flags Affected</h2> |
| <p>The OF, SF, ZF, AF, PF, and CF flags are set according to the result.</p> |
| <h2>Protected Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#GP(0)</td> |
| <td> |
| <p>If the destination is located in a non-writable segment.</p> |
| <p>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</p> |
| <p>If the DS, ES, FS, or GS register contains a NULL segment selector.</p></td></tr> |
| <tr> |
| <td>#SS(0)</td> |
| <td>If a memory operand effective address is outside the SS segment limit.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>If a page fault occurs.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table> |
| <h2>Real-Address Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#GP</td> |
| <td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr> |
| <tr> |
| <td>#SS</td> |
| <td>If a memory operand effective address is outside the SS segment limit.</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table> |
| <h2>Virtual-8086 Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr> |
| <tr> |
| <td>#SS(0)</td> |
| <td>If a memory operand effective address is outside the SS segment limit.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>If a page fault occurs.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table> |
| <h2>Compatibility Mode Exceptions</h2> |
| <p>Same exceptions as in protected mode.</p> |
| <h2>64-Bit Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#SS(0)</td> |
| <td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If the memory address is in a non-canonical form.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>If a page fault occurs.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table></body></html> |