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| <title>SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value </title></head> |
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| <h1>SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value</h1> |
| <table> |
| <tr> |
| <th>Opcode*/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 bit Mode Support</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>F2 0F 51 /<em>r</em></p> |
| <p>SQRTSD <em>xmm1</em>, <em>xmm2/m64</em></p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE2</td> |
| <td>Computes square root of the low double-precision floating-point value in <em>xmm2/m64 </em>and stores the results in <em>xmm1</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.NDS.LIG.F2.0F.WIG 51/r</p> |
| <p>VSQRTSD<em> xmm1,xmm2, xmm3/m64</em></p></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Computes square root of the low double-precision floating point value in <em>xmm3/m64 </em>and stores the results in <em>xmm2</em>. Also, upper double precision floating-point value (bits[127:64]) from <em>xmm2</em> are copied to <em>xmm1</em>[127:64].</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RVM</td> |
| <td>ModRM:reg (w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Computes the square root of the low double-precision floating-point value in the source operand (second operand) and stores the double-precision floating-point result in the destination operand. The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register. The high quadword of the desti-nation operand remains unchanged. See Figure 11-4 in the <em>Intel® 64 and IA-32 Architectures Software Devel-oper’s Manual, Volume 1</em>, for an illustration of a scalar double-precision floating-point operation.</p> |
| <p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p> |
| <p>128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-1:64) of the corresponding YMM destination register remain unchanged.</p> |
| <p>VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p> |
| <h2>Operation</h2> |
| <p><strong>SQRTSD (128-bit Legacy SSE version)</strong></p> |
| <pre>DEST[63:0] ← SQRT(SRC[63:0]) |
| DEST[VLMAX-1:64] (Unmodified)</pre> |
| <p><strong>VSQRTSD (VEX.128 encoded version)</strong></p> |
| <pre>DEST[63:0] ← SQRT(SRC2[63:0]) |
| DEST[127:64] ← SRC1[127:64] |
| DEST[VLMAX-1:128] ← 0</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>SQRTSD:</p> |
| <p>__m128d _mm_sqrt_sd (m128d a, m128d b)</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>Invalid, Precision, Denormal.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 3.</p></body></html> |