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 <h1>SARX/SHLX/SHRX — Shift Without Affecting Flags</h1>
 <table>
 <tr>
 <td>
 <p><strong>Opcode/Instruction</strong></p>
 <p>VEX.NDS<sup>1</sup>.LZ.F3.0F38.W0 F7 /r</p>
 <p>SARX <em>r32a, r/m32, r32b</em></p>
 <p>VEX.NDS<sup>1</sup>.LZ.66.0F38.W0 F7 /r</p>
 <p>SHLX <em>r32a, r/m32, r32b</em></p>
 <p>VEX.NDS<sup>1</sup>.LZ.F2.0F38.W0 F7 /r</p>
 <p>SHRX <em>r32a, r/m32, r32b</em></p>
 <p>VEX.NDS<sup>1</sup>.LZ.F3.0F38.W1 F7 /r</p>
 <p>SARX<em> r64a, r/m64, r64b</em></p>
 <p>VEX.NDS<sup>1</sup>.LZ.66.0F38.W1 F7 /r</p>
 <p>SHLX<em> r64a, r/m64, r64b</em></p>
 <p>VEX.NDS<sup>1</sup>.LZ.F2.0F38.W1 F7 /r</p>
 <p>SHRX <em>r64a, r/m64, r64b</em></p></td>
 <td>
 <p><strong>Op/En</strong></p>
 <p>RMV</p>
 <p>RMV</p>
 <p>RMV</p>
 <p>RMV</p>
 <p>RMV</p>
 <p>RMV</p></td>
 <td>
 <p><strong>64/32 -bit Mode</strong></p>
 <p>V/V</p>
 <p>V/V</p>
 <p>V/V</p>
 <p>V/N.E.</p>
 <p>V/N.E.</p>
 <p>V/N.E.</p></td>
 <td>
 <p><strong>CPUID Feature Flag</strong></p>
 <p>BMI2</p>
 <p>BMI2</p>
 <p>BMI2</p>
 <p>BMI2</p>
 <p>BMI2</p>
 <p>BMI2</p></td>
 <td>
 <p><strong>Description</strong></p>
 <p>Shift <em>r/m32</em> arithmetically right with count specified in <em>r32b.</em></p>
 <p>Shift <em>r/m32</em> logically left with count specified in <em>r32b</em>.</p>
 <p>Shift<em> r/m32</em> logically right with count specified in <em>r32b</em>.</p>
 <p>Shift<em> r/m64</em> arithmetically right with count specified in <em>r64b</em>.</p>
 <p>Shift <em>r/m64</em> logically left with count specified in <em>r64b</em>.</p>
 <p>Shift <em>r/m64</em> logically right with count specified in<em> r64b</em>.</p></td></tr></table>
 <p><strong>NOTES:</strong></p>
 <p>1. ModRM:r/m is used to encode the first source operand (second operand) and VEX.vvvv encodes the second source operand (third oper-</p>
 <p>and).</p>
 <h3>Instruction Operand Encoding</h3>
 <table>
 <tr>
 <td>Op/En</td>
 <td>Operand 1</td>
 <td>Operand 2</td>
 <td>Operand 3</td>
 <td>Operand 4</td></tr>
 <tr>
 <td>RMV</td>
 <td>ModRM:reg (w)</td>
 <td>ModRM:r/m (r)</td>
 <td>VEX.vvvv (r)</td>
 <td>NA</td></tr></table>
 <h2>Description</h2>
 <p>Shifts the bits of the first source operand (the second operand) to the left or right by a COUNT value specified in the second source operand (the third operand). The result is written to the destination operand (the first operand).</p>
 <p>The shift arithmetic right (SARX) and shift logical right (SHRX) instructions shift the bits of the destination operand to the right (toward less significant bit locations), SARX keeps and propagates the most significant bit (sign bit) while shifting.</p>
 <p>The logical shift left (SHLX) shifts the bits of the destination operand to the left (toward more significant bit loca-tions).</p>
 <p>This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.</p>
 <p>If the value specified in the first source operand exceeds OperandSize -1, the COUNT value is masked.</p>
 <p>SARX,SHRX, and SHLX instructions do not update flags.</p>
 <h2>Operation</h2>
 <pre>TEMP ← SRC1;
 IF VEX.W1 and CS.L = 1
 THEN
     countMASK ←3FH;
 ELSE
     countMASK ←1FH;
 FI
 COUNT ← (SRC2 AND countMASK)
 DEST[OperandSize -1] = TEMP[OperandSize -1];
 DO WHILE (COUNT ≠ 0)
     IF instruction is SHLX
          THEN
               DEST[] ← DEST *2;
          ELSE IF instruction is SHRX
               THEN
                     DEST[] ← DEST /2; //unsigned divide
          ELSE
                          // SARX
                     DEST[] ← DEST /2; // signed divide, round toward negative infinity
     FI;
     COUNT ← COUNT - 1;
 OD</pre>
 <h2>Flags Affected</h2>
 <p>None.</p>
 <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
 <p>Auto-generated from high-level language.</p>
 <h2>SIMD Floating-Point Exceptions</h2>
 <p>None</p>
 <h2>Other Exceptions</h2>
 <p>See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally</p>
 <table class="exception-table">
 <tr>
 <td>#UD</td>
 <td>If VEX.W = 1.</td></tr></table></body></html>
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	<head>
	<meta charset="UTF-8">
	<link href="style.css" type="text/css" rel="stylesheet">
	<title>SARX/SHLX/SHRX — Shift Without Affecting Flags </title></head>
	<body>
	<h1>SARX/SHLX/SHRX — Shift Without Affecting Flags</h1>
	<table>
	<tr>
	<td>
	<p><strong>Opcode/Instruction</strong></p>
	<p>VEX.NDS<sup>1</sup>.LZ.F3.0F38.W0 F7 /r</p>
	<p>SARX <em>r32a, r/m32, r32b</em></p>
	<p>VEX.NDS<sup>1</sup>.LZ.66.0F38.W0 F7 /r</p>
	<p>SHLX <em>r32a, r/m32, r32b</em></p>
	<p>VEX.NDS<sup>1</sup>.LZ.F2.0F38.W0 F7 /r</p>
	<p>SHRX <em>r32a, r/m32, r32b</em></p>
	<p>VEX.NDS<sup>1</sup>.LZ.F3.0F38.W1 F7 /r</p>
	<p>SARX<em> r64a, r/m64, r64b</em></p>
	<p>VEX.NDS<sup>1</sup>.LZ.66.0F38.W1 F7 /r</p>
	<p>SHLX<em> r64a, r/m64, r64b</em></p>
	<p>VEX.NDS<sup>1</sup>.LZ.F2.0F38.W1 F7 /r</p>
	<p>SHRX <em>r64a, r/m64, r64b</em></p></td>
	<td>
	<p><strong>Op/En</strong></p>
	<p>RMV</p>
	<p>RMV</p>
	<p>RMV</p>
	<p>RMV</p>
	<p>RMV</p>
	<p>RMV</p></td>
	<td>
	<p><strong>64/32 -bit Mode</strong></p>
	<p>V/V</p>
	<p>V/V</p>
	<p>V/V</p>
	<p>V/N.E.</p>
	<p>V/N.E.</p>
	<p>V/N.E.</p></td>
	<td>
	<p><strong>CPUID Feature Flag</strong></p>
	<p>BMI2</p>
	<p>BMI2</p>
	<p>BMI2</p>
	<p>BMI2</p>
	<p>BMI2</p>
	<p>BMI2</p></td>
	<td>
	<p><strong>Description</strong></p>
	<p>Shift <em>r/m32</em> arithmetically right with count specified in <em>r32b.</em></p>
	<p>Shift <em>r/m32</em> logically left with count specified in <em>r32b</em>.</p>
	<p>Shift<em> r/m32</em> logically right with count specified in <em>r32b</em>.</p>
	<p>Shift<em> r/m64</em> arithmetically right with count specified in <em>r64b</em>.</p>
	<p>Shift <em>r/m64</em> logically left with count specified in <em>r64b</em>.</p>
	<p>Shift <em>r/m64</em> logically right with count specified in<em> r64b</em>.</p></td></tr></table>
	<p><strong>NOTES:</strong></p>
	<p>1. ModRM:r/m is used to encode the first source operand (second operand) and VEX.vvvv encodes the second source operand (third oper-</p>
	<p>and).</p>
	<h3>Instruction Operand Encoding</h3>
	<table>
	<tr>
	<td>Op/En</td>
	<td>Operand 1</td>
	<td>Operand 2</td>
	<td>Operand 3</td>
	<td>Operand 4</td></tr>
	<tr>
	<td>RMV</td>
	<td>ModRM:reg (w)</td>
	<td>ModRM:r/m (r)</td>
	<td>VEX.vvvv (r)</td>
	<td>NA</td></tr></table>
	<h2>Description</h2>
	<p>Shifts the bits of the first source operand (the second operand) to the left or right by a COUNT value specified in the second source operand (the third operand). The result is written to the destination operand (the first operand).</p>
	<p>The shift arithmetic right (SARX) and shift logical right (SHRX) instructions shift the bits of the destination operand to the right (toward less significant bit locations), SARX keeps and propagates the most significant bit (sign bit) while shifting.</p>
	<p>The logical shift left (SHLX) shifts the bits of the destination operand to the left (toward more significant bit loca-tions).</p>
	<p>This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.</p>
	<p>If the value specified in the first source operand exceeds OperandSize -1, the COUNT value is masked.</p>
	<p>SARX,SHRX, and SHLX instructions do not update flags.</p>
	<h2>Operation</h2>
	<pre>TEMP ← SRC1;
	IF VEX.W1 and CS.L = 1
	THEN
	countMASK ←3FH;
	ELSE
	countMASK ←1FH;
	FI
	COUNT ← (SRC2 AND countMASK)
	DEST[OperandSize -1] = TEMP[OperandSize -1];
	DO WHILE (COUNT ≠ 0)
	IF instruction is SHLX
	THEN
	DEST[] ← DEST *2;
	ELSE IF instruction is SHRX
	THEN
	DEST[] ← DEST /2; //unsigned divide
	ELSE
	// SARX
	DEST[] ← DEST /2; // signed divide, round toward negative infinity
	FI;
	COUNT ← COUNT - 1;
	OD</pre>
	<h2>Flags Affected</h2>
	<p>None.</p>
	<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
	<p>Auto-generated from high-level language.</p>
	<h2>SIMD Floating-Point Exceptions</h2>
	<p>None</p>
	<h2>Other Exceptions</h2>
	<p>See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally</p>
	<table class="exception-table">
	<tr>
	<td>#UD</td>
	<td>If VEX.W = 1.</td></tr></table></body></html>