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| <title>RORX — Rotate Right Logical Without Affecting Flags </title></head> |
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| <h1>RORX — Rotate Right Logical Without Affecting Flags</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 -bit Mode</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>VEX.LZ.F2.0F3A.W0 F0 /r ib</p> |
| <p>RORX r32, <em>r/m32, imm8</em></p></td> |
| <td>RMI</td> |
| <td>V/V</td> |
| <td>BMI2</td> |
| <td>Rotate 32-bit <em>r/m32</em> right <em>imm8</em> times without affecting arithmetic flags.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.LZ.F2.0F3A.W1 F0 /r ib</p> |
| <p>RORX r64, <em>r/m64, imm8</em></p></td> |
| <td>RMI</td> |
| <td>V/N.E.</td> |
| <td>BMI2</td> |
| <td>Rotate 64-bit <em>r/m64</em> right <em>imm8</em> times without affecting arithmetic flags.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RMI</td> |
| <td>ModRM:reg (w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>Imm8</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Rotates the bits of second operand right by the count value specified in imm8 without affecting arithmetic flags. The RORX instruction does not read or write the arithmetic flags.</p> |
| <p>This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.</p> |
| <h2>Operation</h2> |
| <pre>IF (OperandSize = 32) |
| y ← imm8 AND 1FH; |
| DEST ← (SRC >> y) | (SRC << (32-y)); |
| ELSEIF (OperandSize = 64 ) |
| y ← imm8 AND 3FH; |
| DEST ← (SRC >> y) | (SRC << (64-y)); |
| ENDIF</pre> |
| <h2>Flags Affected</h2> |
| <p>None</p> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>Auto-generated from high-level language.</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>None</p> |
| <h2>Other Exceptions</h2> |
| <p>See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally</p> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td>If VEX.W = 1.</td></tr></table></body></html> |