views/asm-docs-source/RDMSR.html - compiler-explorer - Rivoreo Source Code Repositories

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 <title>RDMSR—Read from Model Specific Register </title></head>
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 <h1>RDMSR—Read from Model Specific Register</h1>
 <table>
 <tr>
 <th>Opcode*</th>
 <th>Instruction</th>
 <th>Op/En</th>
 <th>64-Bit Mode</th>
 <th>Compat/Leg Mode</th>
 <th>Description</th></tr>
 <tr>
 <td>0F 32</td>
 <td>RDMSR</td>
 <td>NP</td>
 <td>Valid</td>
 <td>Valid</td>
 <td>Read MSR specified by ECX into EDX:EAX.</td></tr></table>
 <p><strong>NOTES:</strong></p>
 <p>*</p>
 <p>See IA-32 Architecture Compatibility section below.</p>
 <h3>Instruction Operand Encoding</h3>
 <table>
 <tr>
 <td>Op/En</td>
 <td>Operand 1</td>
 <td>Operand 2</td>
 <td>Operand 3</td>
 <td>Operand 4</td></tr>
 <tr>
 <td>NP</td>
 <td>NA</td>
 <td>NA</td>
 <td>NA</td>
 <td>NA</td></tr></table>
 <h2>Description</h2>
 <p>Reads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If fewer than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined.</p>
 <p>This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.</p>
 <p>The MSRs control functions for testability, execution tracing, performance-monitoring, and machine check errors. Chapter 35, “Model-Specific Registers (MSRs),” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C</em>, lists all the MSRs that can be read with this instruction and their addresses. Note that each processor family has its own set of MSRs.</p>
 <p>The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before using this instruction.</p>
 <h2>IA-32 Architecture Compatibility</h2>
 <p>The MSRs and the ability to read them with the RDMSR instruction were introduced into the IA-32 Architecture with the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor results in an invalid opcode exception #UD.</p>
 <p>See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the <em>Intel® 64 and IA-32 Archi-tectures Software Developer’s Manual, Volume 3C</em>, for more information about the behavior of this instruction in VMX non-root operation.</p>
 <h2>Operation</h2>
 <pre>EDX:EAX ← MSR[ECX];</pre>
 <h2>Flags Affected</h2>
 <p>None.</p>
 <h2>Protected Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP(0)</td>
 <td>
 <p>If the current privilege level is not 0.</p>
 <p>If the value in ECX specifies a reserved or unimplemented MSR address.</p></td></tr>
 <tr>
 <td>#UD</td>
 <td>If the LOCK prefix is used.</td></tr></table>
 <h2>Real-Address Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP</td>
 <td>If the value in ECX specifies a reserved or unimplemented MSR address.</td></tr>
 <tr>
 <td>#UD</td>
 <td>If the LOCK prefix is used.</td></tr></table>
 <h2>Virtual-8086 Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP(0)</td>
 <td> The RDMSR instruction is not recognized in virtual-8086 mode.</td></tr></table>
 <h2>Compatibility Mode Exceptions</h2>
 <p>Same exceptions as in protected mode.</p>
 <h2>64-Bit Mode Exceptions</h2>
 <p>Same exceptions as in protected mode.</p></body></html>
	<!DOCTYPE html>

	<html>
	<head>
	<meta charset="UTF-8">
	<link href="style.css" type="text/css" rel="stylesheet">
	<title>RDMSR—Read from Model Specific Register </title></head>
	<body>
	<h1>RDMSR—Read from Model Specific Register</h1>
	<table>
	<tr>
	<th>Opcode*</th>
	<th>Instruction</th>
	<th>Op/En</th>
	<th>64-Bit Mode</th>
	<th>Compat/Leg Mode</th>
	<th>Description</th></tr>
	<tr>
	<td>0F 32</td>
	<td>RDMSR</td>
	<td>NP</td>
	<td>Valid</td>
	<td>Valid</td>
	<td>Read MSR specified by ECX into EDX:EAX.</td></tr></table>
	<p><strong>NOTES:</strong></p>
	<p>*</p>
	<p>See IA-32 Architecture Compatibility section below.</p>
	<h3>Instruction Operand Encoding</h3>
	<table>
	<tr>
	<td>Op/En</td>
	<td>Operand 1</td>
	<td>Operand 2</td>
	<td>Operand 3</td>
	<td>Operand 4</td></tr>
	<tr>
	<td>NP</td>
	<td>NA</td>
	<td>NA</td>
	<td>NA</td>
	<td>NA</td></tr></table>
	<h2>Description</h2>
	<p>Reads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If fewer than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined.</p>
	<p>This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.</p>
	<p>The MSRs control functions for testability, execution tracing, performance-monitoring, and machine check errors. Chapter 35, “Model-Specific Registers (MSRs),” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C</em>, lists all the MSRs that can be read with this instruction and their addresses. Note that each processor family has its own set of MSRs.</p>
	<p>The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before using this instruction.</p>
	<h2>IA-32 Architecture Compatibility</h2>
	<p>The MSRs and the ability to read them with the RDMSR instruction were introduced into the IA-32 Architecture with the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor results in an invalid opcode exception #UD.</p>
	<p>See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the <em>Intel® 64 and IA-32 Archi-tectures Software Developer’s Manual, Volume 3C</em>, for more information about the behavior of this instruction in VMX non-root operation.</p>
	<h2>Operation</h2>
	<pre>EDX:EAX ← MSR[ECX];</pre>
	<h2>Flags Affected</h2>
	<p>None.</p>
	<h2>Protected Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP(0)</td>
	<td>
	<p>If the current privilege level is not 0.</p>
	<p>If the value in ECX specifies a reserved or unimplemented MSR address.</p></td></tr>
	<tr>
	<td>#UD</td>
	<td>If the LOCK prefix is used.</td></tr></table>
	<h2>Real-Address Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP</td>
	<td>If the value in ECX specifies a reserved or unimplemented MSR address.</td></tr>
	<tr>
	<td>#UD</td>
	<td>If the LOCK prefix is used.</td></tr></table>
	<h2>Virtual-8086 Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP(0)</td>
	<td> The RDMSR instruction is not recognized in virtual-8086 mode.</td></tr></table>
	<h2>Compatibility Mode Exceptions</h2>
	<p>Same exceptions as in protected mode.</p>
	<h2>64-Bit Mode Exceptions</h2>
	<p>Same exceptions as in protected mode.</p></body></html>