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<title>PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical </title></head>
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<h1>PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical</h1>
<p><strong>Description</strong></p>
<p><strong>CPUID</strong></p>
<p><strong>Opcode/</strong></p>
<p><strong>Op/</strong></p>
<p><strong>64/32 bit</strong></p>
<p><strong>Feature</strong></p>
<p><strong>Instruction</strong></p>
<p><strong>En</strong></p>
<p><strong>Mode</strong></p>
<p><strong>Flag</strong></p>
<p><strong>Support</strong></p>
<p>0F F1 /<em>r</em><sup>1</sup></p>
<p>RM</p>
<p>V/V</p>
<p>MMX</p>
<p>Shift words in <em>mm</em> left <em>mm/m64</em> while shifting in 0s.</p>
<p>PSLLW <em>mm, mm/m64</em></p>
<p>66 0F F1 /<em>r</em></p>
<p>RM</p>
<p>V/V</p>
<p>SSE2</p>
<p>Shift words in <em>xmm1</em> left by <em>xmm2/m128 </em>while shifting in 0s.</p>
<p>PSLLW <em>xmm1</em>, <em>xmm2/m128</em></p>
<p>0F 71 /6 ib</p>
<p>MI</p>
<p>V/V</p>
<p>MMX</p>
<p>Shift words in <em>mm</em> left by <em>imm8</em> while shifting in 0s.</p>
<p>PSLLW <em>mm1</em>, <em>imm8</em></p>
<p>66 0F 71 /6 ib</p>
<p>MI</p>
<p>V/V</p>
<p>SSE2</p>
<p>Shift words in <em>xmm1</em> left by <em>imm8</em> while shifting in 0s.</p>
<p>PSLLW <em>xmm1</em>, <em>imm8</em></p>
<p>RM</p>
<p>V/V</p>
<p>MMX</p>
<p>Shift doublewords in <em>mm</em> left by <em>mm/m64</em></p>
<p>0F F2 /<em>r</em><sup>1</sup></p>
<p>while shifting in 0s.</p>
<p>PSLLD<em> mm, mm/m64</em></p>
<p>66 0F F2 /<em>r</em></p>
<p>RM</p>
<p>V/V</p>
<p>SSE2</p>
<p>Shift doublewords in <em>xmm1</em> left by <em>xmm2/m128</em> while shifting in 0s.</p>
<p>PSLLD <em>xmm1</em>, <em>xmm2/m128</em></p>
<p>0F 72 /6 ib<sup>1</sup></p>
<p>MI</p>
<p>V/V</p>
<p>MMX</p>
<p>Shift doublewords in <em>mm</em> left by <em>imm8</em> while shifting in 0s.</p>
<p>PSLLD <em>mm, imm8</em></p>
<p>66 0F 72 /6 ib</p>
<p>MI</p>
<p>V/V</p>
<p>SSE2</p>
<p>Shift doublewords in <em>xmm1</em> left by <em>imm8</em> while shifting in 0s.</p>
<p>PSLLD <em>xmm1</em>, <em>imm8</em></p>
<p>RM</p>
<p>V/V</p>
<p>MMX</p>
<p>Shift quadword in <em>mm</em> left by <em>mm/m64 </em>while</p>
<p>0F F3 /<em>r</em><sup>1</sup></p>
<p>shifting in 0s.</p>
<p>PSLLQ <em>mm, mm/m64</em></p>
<p>66 0F F3 /<em>r</em></p>
<p>RM</p>
<p>V/V</p>
<p>SSE2</p>
<p>Shift quadwords in <em>xmm1</em> left by <em>xmm2/m128 </em>while shifting in 0s.</p>
<p>PSLLQ <em>xmm1</em>, <em>xmm2/m128</em></p>
<p>MI</p>
<p>V/V</p>
<p>MMX</p>
<p>Shift quadword in <em>mm</em> left by <em>imm8</em> while</p>
<p>0F 73 /6 ib<sup>1</sup></p>
<p>shifting in 0s.</p>
<p>PSLLQ <em>mm, imm8</em></p>
<p>66 0F 73 /6 ib</p>
<p>MI</p>
<p>V/V</p>
<p>SSE2</p>
<p>Shift quadwords in <em>xmm1</em> left by <em>imm8</em> while shifting in 0s.</p>
<p>PSLLQ <em>xmm1</em>, <em>imm8</em></p>
<p>VEX.NDS.128.66.0F.WIG F1 /r</p>
<p>RVM</p>
<p>V/V</p>
<p>AVX</p>
<p>Shift words in <em>xmm2</em> left by amount specified in <em>xmm3/m128 </em>while shifting in 0s.</p>
<p>VPSLLW <em>xmm1, xmm2, xmm3/m128</em></p>
<p>VEX.NDD.128.66.0F.WIG 71 /6 ib</p>
<p>VMI</p>
<p>V/V</p>
<p>AVX</p>
<p>Shift words in <em>xmm2</em> left by <em>imm8</em> while shifting in 0s.</p>
<p>VPSLLW <em>xmm1, xmm2, imm8</em></p>
<p>VEX.NDS.128.66.0F.WIG F2 /r</p>
<p>RVM</p>
<p>V/V</p>
<p>AVX</p>
<p>Shift doublewords in <em>xmm2</em> left by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p>
<p>VPSLLD <em>xmm1, xmm2, xmm3/m128</em></p>
<p>VEX.NDD.128.66.0F.WIG 72 /6 ib</p>
<p>VMI</p>
<p>V/V</p>
<p>AVX</p>
<p>Shift doublewords in <em>xmm2 </em>left by<em> imm8 </em>while shifting in 0s.</p>
<p>VPSLLD <em>xmm1, xmm2, imm8</em></p>
<p>VEX.NDS.128.66.0F.WIG F3 /r</p>
<p>RVM</p>
<p>V/V</p>
<p>AVX</p>
<p>Shift quadwords in <em>xmm2</em> left by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p>
<p>VPSLLQ <em>xmm1, xmm2, xmm3/m128</em></p>
<p>VEX.NDD.128.66.0F.WIG 73 /6 ib</p>
<p>VMI</p>
<p>V/V</p>
<p>AVX</p>
<p>Shift quadwords in <em>xmm2</em> left by<em> imm8</em> while shifting in 0s.</p>
<p>VPSLLQ <em>xmm1, xmm2, imm8</em></p>
<p>VEX.NDS.256.66.0F.WIG F1 /r</p>
<p>RVM</p>
<p>V/V</p>
<p>AVX2</p>
<p>Shift words in <em>ymm2</em> left by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p>
<p>VPSLLW <em>ymm1, ymm2, xmm3/m128</em></p>
<p>VEX.NDD.256.66.0F.WIG 71 /6 ib</p>
<p>VMI</p>
<p>V/V</p>
<p>AVX2</p>
<p>Shift words in <em>ymm2</em> left by <em>imm8</em> while shifting in 0s.</p>
<p>VPSLLW <em>ymm1, ymm2, imm8</em></p>
<p>VEX.NDS.256.66.0F.WIG F2 /r</p>
<p>RVM</p>
<p>V/V</p>
<p>AVX2</p>
<p>Shift doublewords in <em>ymm2</em> left by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p>
<p>VPSLLD <em>ymm1, ymm2, xmm3/m128</em></p>
<p>VEX.NDD.256.66.0F.WIG 72 /6 ib</p>
<p>VMI</p>
<p>V/V</p>
<p>AVX2</p>
<p>Shift doublewords in <em>ymm2</em> left by<em> imm8 </em>while shifting in 0s.</p>
<p>VPSLLD <em>ymm1, ymm2, imm8</em></p>
<p>VEX.NDS.256.66.0F.WIG F3 /r</p>
<p>RVM</p>
<p>V/V</p>
<p>AVX2</p>
<p>Shift quadwords in <em>ymm2</em> left by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p>
<p>VPSLLQ <em>ymm1, ymm2, xmm3/m128</em></p>
<p>VEX.NDD.256.66.0F.WIG 73 /6 ib</p>
<p>VMI</p>
<p>V/V</p>
<p>AVX2</p>
<p>Shift quadwords in <em>ymm2</em> left by <em>imm8</em> while shifting in 0s.</p>
<p>VPSLLQ <em>ymm1, ymm2, imm8</em></p>
<p>NOTES:</p>
<p>1. See note in Section 2.4, “Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>MI</td>
<td>ModRM:r/m (r, w)</td>
<td>imm8</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>VMI</td>
<td>VEX.vvvv (w)</td>
<td>ModRM:r/m (r)</td>
<td>imm8</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first operand) to the left by the number of bits specified in the count operand (second operand). As the bits in the data elements are shifted left, the empty low-order bits are cleared (set to 0). If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand is set to all 0s. Figure 4-13 gives an example of shifting words in a 64-bit operand.</p>
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<text y="640461.107384" x="197.0398" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="53.5835">X3 &lt;&lt; COUNT</text></svg>
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<text y="640461.107384" x="260.8201" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="53.5832">X2 &lt;&lt; COUNT</text>
<text y="640461.107384" x="324.0599" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="53.5834">X1 &lt;&lt; COUNT</text>
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<h3>Figure 4-13. PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit Operand</h3>
<p>The (V)PSLLW instruction shifts each of the words in the destination operand to the left by the number of bits spec-ified in the count operand; the (V)PSLLD instruction shifts each of the doublewords in the destination operand; and the (V)PSLLQ instruction shifts the quadword (or quadwords) in the destination operand.</p>
<p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>Legacy SSE instructions: The destination operand is an MMX technology register; the count operand can be either an MMX technology register or an 64-bit memory location.</p>
<p>128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged. The count operand can be either an XMM register or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are ignored.</p>
<p>VEX.128 encoded version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register are zeroed. The count operand can be either an XMM register or a 128-bit memory loca-tion or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are ignored.</p>
<p>VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be either an XMM register or a 128-bit memory location or an 8-bit immediate.</p>
<p>Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /6), VEX.vvvv encodes the destination register, and VEX.B + ModRM.r/m encodes the source register. VEX.L must be 0, otherwise instructions will #UD.</p>
<h2>Operation</h2>
<p><strong>PSLLW (with 64-bit operand)</strong></p>
<pre> IF (COUNT &gt; 15)
THEN
DEST[64:0] ← 0000000000000000H;
ELSE
DEST[15:0] ← ZeroExtend(DEST[15:0] &lt;&lt; COUNT);
(* Repeat shift operation for 2nd and 3rd words *)
DEST[63:48] ← ZeroExtend(DEST[63:48] &lt;&lt; COUNT);
FI;</pre>
<p><strong>PSLLD (with 64-bit operand)</strong></p>
<pre> IF (COUNT &gt; 31)
THEN
DEST[64:0] ← 0000000000000000H;
ELSE
DEST[31:0] ← ZeroExtend(DEST[31:0] &lt;&lt; COUNT);
DEST[63:32] ← ZeroExtend(DEST[63:32] &lt;&lt; COUNT);
FI;</pre>
<p><strong>PSLLQ (with 64-bit operand)</strong></p>
<pre> IF (COUNT &gt; 63)
THEN
DEST[64:0] ← 0000000000000000H;
ELSE
DEST ← ZeroExtend(DEST &lt;&lt; COUNT);
FI;</pre>
<p><strong>PSLLW (with 128-bit operand)</strong></p>
<pre> COUNT ← COUNT_SOURCE[63:0];
IF (COUNT &gt; 15)
THEN
DEST[128:0] ← 00000000000000000000000000000000H;
ELSE
DEST[15:0] ← ZeroExtend(DEST[15:0] &lt;&lt; COUNT);
(* Repeat shift operation for 2nd through 7th words *)
DEST[127:112] ← ZeroExtend(DEST[127:112] &lt;&lt; COUNT);
FI;</pre>
<p><strong>PSLLD (with 128-bit operand)</strong></p>
<pre> COUNT ← COUNT_SOURCE[63:0];
IF (COUNT &gt; 31)
THEN
DEST[128:0] ← 00000000000000000000000000000000H;
ELSE
DEST[31:0] ← ZeroExtend(DEST[31:0] &lt;&lt; COUNT);
(* Repeat shift operation for 2nd and 3rd doublewords *)
DEST[127:96] ← ZeroExtend(DEST[127:96] &lt;&lt; COUNT);
FI;</pre>
<p><strong>PSLLQ (with 128-bit operand)</strong></p>
<pre> COUNT ← COUNT_SOURCE[63:0];
IF (COUNT &gt; 63)
THEN
DEST[128:0] ← 00000000000000000000000000000000H;
ELSE
DEST[63:0] ← ZeroExtend(DEST[63:0] &lt;&lt; COUNT);
DEST[127:64] ← ZeroExtend(DEST[127:64] &lt;&lt; COUNT);
FI;</pre>
<p><strong>PSLLW (xmm, xmm, xmm/m128)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_WORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>PSLLW (xmm, imm8)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_WORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>VPSLLD (xmm, xmm, xmm/m128)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_DWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] ← 0</pre>
<p><strong>VPSLLD (xmm, imm8)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_DWORDS(SRC1, imm8)
DEST[VLMAX-1:128] ← 0</pre>
<p><strong>PSLLD (xmm, xmm, xmm/m128)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_DWORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>PSLLD (xmm, imm8)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_DWORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>VPSLLQ (xmm, xmm, xmm/m128)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_QWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] ← 0</pre>
<p><strong>VPSLLQ (xmm, imm8)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_QWORDS(SRC1, imm8)
DEST[VLMAX-1:128] ← 0</pre>
<p><strong>PSLLQ (xmm, xmm, xmm/m128)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_QWORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>PSLLQ (xmm, imm8)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_QWORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>VPSLLW (xmm, xmm, xmm/m128)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_WORDS(SRC1, SRC2)
DEST[VLMAX-1:128] ← 0</pre>
<p><strong>VPSLLW (xmm, imm8)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_WORDS(SRC1, imm8)
DEST[VLMAX-1:128] ← 0</pre>
<p><strong>PSLLW (xmm, xmm, xmm/m128)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_WORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>PSLLW (xmm, imm8)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_WORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>VPSLLD (xmm, xmm, xmm/m128)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_DWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] ← 0</pre>
<p><strong>VPSLLD (xmm, imm8)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_DWORDS(SRC1, imm8)
DEST[VLMAX-1:128] ← 0</pre>
<p><strong>VPSLLW (ymm, ymm, xmm/m128)</strong></p>
<pre>DEST[255:0] ← LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1, SRC2)</pre>
<p><strong>VPSLLW (ymm, imm8)</strong></p>
<pre>DEST[255:0] ← LOGICAL_LEFT_SHIFT_WORD_256bS(SRC1, imm8)</pre>
<p><strong>VPSLLD (ymm, ymm, xmm/m128)</strong></p>
<pre>DEST[255:0] ← LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, SRC2)</pre>
<p><strong>VPSLLD (ymm, imm8)</strong></p>
<pre>DEST[127:0] ← LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, imm8)</pre>
<p><strong>VPSLLQ (ymm, ymm, xmm/m128)</strong></p>
<pre>DEST[255:0] ← LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, SRC2)</pre>
<p><strong>VPSLLQ (ymm, imm8)</strong></p>
<pre>DEST[255:0] ← LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, imm8)</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalents</h2>
<p>PSLLW:</p>
<p>__m64 _mm_slli_pi16 (__m64 m, int count)</p>
<p>PSLLW:</p>
<p>__m64 _mm_sll_pi16(__m64 m, __m64 count)</p>
<p>(V)PSLLW:</p>
<p>__m128i _mm_slli_pi16(__m64 m, int count)</p>
<p>(V)PSLLW:</p>
<p>__m128i _mm_slli_pi16(__m128i m, __m128i count)</p>
<p>VPSLLW:</p>
<p>__m256i _mm256_slli_epi16 (__m256i m, int count)</p>
<p>VPSLLW:</p>
<p>__m256i _mm256_sll_epi16 (__m256i m, __m128i count)</p>
<p>PSLLD:</p>
<p>__m64 _mm_slli_pi32(__m64 m, int count)</p>
<p>PSLLD:</p>
<p>__m64 _mm_sll_pi32(__m64 m, __m64 count)</p>
<p>(V)PSLLD:</p>
<p>__m128i _mm_slli_epi32(__m128i m, int count)</p>
<p>(V)PSLLD:</p>
<p>__m128i _mm_sll_epi32(__m128i m, __m128i count)</p>
<p>VPSLLD:</p>
<p>__m256i _mm256_slli_epi32 (__m256i m, int count)</p>
<p>VPSLLD:</p>
<p>__m256i _mm256_sll_epi32 (__m256i m, __m128i count)</p>
<p>PSLLQ:</p>
<p>__m64 _mm_slli_si64(__m64 m, int count)</p>
<p>PSLLQ:</p>
<p>__m64 _mm_sll_si64(__m64 m, __m64 count)</p>
<p>(V)PSLLQ:</p>
<p>__m128i _mm_slli_epi64(__m128i m, int count)</p>
<p>(V)PSLLQ:</p>
<p>__m128i _mm_sll_epi64(__m128i m, __m128i count)</p>
<p>VPSLLQ:</p>
<p>__m256i _mm256_slli_epi64 (__m256i m, int count)</p>
<p>VPSLLQ:</p>
<p>__m256i _mm256_sll_epi64 (__m256i m, __m128i count)</p>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>Numeric Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>See Exceptions Type 4 and 7 for non-VEX-encoded instructions; additionally</p>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>If VEX.L = 1.</td></tr></table></body></html>