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| <title>PSHUFD—Shuffle Packed Doublewords </title></head> |
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| <h1>PSHUFD—Shuffle Packed Doublewords</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 bit Mode Support</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>66 0F 70 /<em>r</em> ib</p> |
| <p>PSHUFD <em>xmm1</em>, <em>xmm2/m128</em>, <em>imm8</em></p></td> |
| <td>RMI</td> |
| <td>V/V</td> |
| <td> SSE2</td> |
| <td>Shuffle the doublewords in <em>xmm2/m128 </em>based on the encoding in <em>imm8</em> and store the result in <em>xmm1</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.128.66.0F.WIG 70 /r ib</p> |
| <p>VPSHUFD <em>xmm1, xmm2/m128, imm8</em></p></td> |
| <td>RMI</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Shuffle the doublewords in <em>xmm2/m128 </em>based on the encoding in <em>imm8</em> and store the result in <em>xmm1</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.256.66.0F.WIG 70 /r ib</p> |
| <p>VPSHUFD <em>ymm1, ymm2/m256, imm8</em></p></td> |
| <td>RMI</td> |
| <td>V/V</td> |
| <td>AVX2</td> |
| <td>Shuffle the doublewords in <em>ymm2/m256 </em>based on the encoding in <em>imm8</em> and store the result in <em>ymm1</em>.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RMI</td> |
| <td>ModRM:reg (w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>imm8</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Copies doublewords from source operand (second operand) and inserts them in the destination operand (first operand) at the locations selected with the order operand (third operand). Figure 4-12 shows the operation of the 256-bit VPSHUFD instruction and the encoding of the order operand. Each 2-bit field in the order operand selects the contents of one doubleword location within a 128-bit lane and copy to the target element in the destination operand. For example, bits 0 and 1 of the order operand targets the first doubleword element in the low and high 128-bit lane of the destination operand for 256-bit VPSHUFD. The encoded value of bits 1:0 of the order operand (see the field encoding in Figure 4-12) determines which doubleword element (from the respective 128-bit lane) of the source operand will be copied to doubleword 0 of the destination operand.</p> |
| <p>For 128-bit operation, only the low 128-bit lane are operative. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword location in the destination operand.</p> |
| <p>SRC</p> |
| <p>X7</p> |
| <p>X6</p> |
| <p>X5</p> |
| <p>X4</p> |
| <p>X3</p> |
| <p>X2</p> |
| <p>X1</p> |
| <p>X0</p> |
| <p>DEST</p> |
| <p>Y7</p> |
| <p>Y6</p> |
| <p>Y5</p> |
| <p>Y4</p> |
| <p>Y3</p> |
| <p>Y2</p> |
| <p>Y1</p> |
| <p>Y0</p> |
| <p>00B - X4</p> |
| <p>Encoding</p> |
| <p>00B - X0</p> |
| <p>Encoding</p> |
| <p>01B - X5</p> |
| <p>of Fields in</p> |
| <p>ORDER</p> |
| <p>01B - X1</p> |
| <p>of Fields in</p> |
| <p>10B - X6</p> |
| <p>ORDER</p> |
| <p>10B - X2</p> |
| <p>ORDER</p> |
| <p>11B - X7</p> |
| <p>Operand</p> |
| <p>7</p> |
| <p>56</p> |
| <p>4</p> |
| <p>3</p> |
| <p>12</p> |
| <p>0</p> |
| <p>11B - X3</p> |
| <p>Operand</p> |
| <h3>Figure 4-12. 256-bit VPSHUFD Instruction Operation</h3> |
| <p>The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword location in the destination operand.</p> |
| <p>Legacy SSE instructions: In 64-bit mode using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p> |
| <p>128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p> |
| <p>VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p> |
| <p>VEX.256 encoded version: Bits (255:128) of the destination stores the shuffled results of the upper 16 bytes of the source operand using the immediate byte as the order operand.</p> |
| <p>Note: VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.</p> |
| <h2>Operation</h2> |
| <p><strong>PSHUFD (128-bit Legacy SSE version)</strong></p> |
| <pre>DEST[31:0] ← (SRC >> (ORDER[1:0] * 32))[31:0]; |
| DEST[63:32] ← (SRC >> (ORDER[3:2] * 32))[31:0]; |
| DEST[95:64] ← (SRC >> (ORDER[5:4] * 32))[31:0]; |
| DEST[127:96] ← (SRC >> (ORDER[7:6] * 32))[31:0]; |
| DEST[VLMAX-1:128] (Unmodified)</pre> |
| <p><strong>VPSHUFD (VEX.128 encoded version)</strong></p> |
| <pre>DEST[31:0] ← (SRC >> (ORDER[1:0] * 32))[31:0]; |
| DEST[63:32] ← (SRC >> (ORDER[3:2] * 32))[31:0]; |
| DEST[95:64] ← (SRC >> (ORDER[5:4] * 32))[31:0]; |
| DEST[127:96] ← (SRC >> (ORDER[7:6] * 32))[31:0]; |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VPSHUFD (VEX.256 encoded version)</strong></p> |
| <pre>DEST[31:0] ← (SRC[127:0] >> (ORDER[1:0] * 32))[31:0]; |
| DEST[63:32] ← (SRC[127:0] >> (ORDER[3:2] * 32))[31:0]; |
| DEST[95:64] ← (SRC[127:0] >> (ORDER[5:4] * 32))[31:0]; |
| DEST[127:96] ← (SRC[127:0] >> (ORDER[7:6] * 32))[31:0]; |
| DEST[159:128] ← (SRC[255:128] >> (ORDER[1:0] * 32))[31:0]; |
| DEST[191:160] ← (SRC[255:128] >> (ORDER[3:2] * 32))[31:0]; |
| DEST[223:192] ← (SRC[255:128] >> (ORDER[5:4] * 32))[31:0]; |
| DEST[255:224] ← (SRC[255:128] >> (ORDER[7:6] * 32))[31:0];</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>(V)PSHUFD:</p> |
| <p>__m128i _mm_shuffle_epi32(__m128i a, int n)</p> |
| <p>VPSHUFD:</p> |
| <p>__m256i _mm256_shuffle_epi32(__m256i a, const int n)</p> |
| <h2>Flags Affected</h2> |
| <p>None.</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>None.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 4; additionally</p> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If VEX.L = 1.</p> |
| <p>If VEX.vvvv ≠ 1111B.</p></td></tr></table></body></html> |