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| <title>PMULLD — Multiply Packed Signed Dword Integers and Store Low Result </title></head> |
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| <h1>PMULLD — Multiply Packed Signed Dword Integers and Store Low Result</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 bit Mode Support</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td>66 0F 38 40 /r PMULLD <em>xmm1, xmm2/m128</em></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE4_1</td> |
| <td>Multiply the packed dword signed integers in <em>xmm1</em> and <em>xmm2/m128</em> and store the low 32 bits of each product in <em>xmm1</em>.</td></tr> |
| <tr> |
| <td>VEX.NDS.128.66.0F38.WIG 40 /r VPMULLD <em>xmm1, xmm2, xmm3/m128</em></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Multiply the packed dword signed integers in <em>xmm2</em> and <em>xmm3/m128</em> and store the low 32 bits of each product in <em>xmm1</em>.</td></tr> |
| <tr> |
| <td>VEX.NDS.256.66.0F38.WIG 40 /r VPMULLD <em>ymm1, ymm2, ymm3/m256</em></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX2</td> |
| <td>Multiply the packed dword signed integers in <em>ymm2</em> and <em>ymm3/m256</em> and store the low 32 bits of each product in<em> ymm1</em>.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RVM</td> |
| <td>ModRM:reg (w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Performs four signed multiplications from four pairs of signed dword integers and stores the lower 32 bits of the four 64-bit products in the destination operand (first operand). Each dword element in the destination operand is multiplied with the corresponding dword element of the source operand (second operand) to obtain a 64-bit inter-mediate product.</p> |
| <p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-tion register remain unchanged.</p> |
| <p>VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p> |
| <p>VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.</p> |
| <p>Note: VEX.L must be 0, otherwise the instruction will #UD.</p> |
| <h2>Operation</h2> |
| <pre>Temp0[63:0] ← DEST[31:0] * SRC[31:0]; |
| Temp1[63:0] ← DEST[63:32] * SRC[63:32]; |
| Temp2[63:0] ← DEST[95:64] * SRC[95:64]; |
| Temp3[63:0] ← DEST[127:96] * SRC[127:96]; |
| DEST[31:0] ← Temp0[31:0]; |
| DEST[63:32] ← Temp1[31:0]; |
| DEST[95:64] ← Temp2[31:0]; |
| DEST[127:96] ← Temp3[31:0];</pre> |
| <p><strong>VPMULLD (VEX.128 encoded version)</strong></p> |
| <pre>Temp0[63:0] ← SRC1[31:0] * SRC2[31:0] |
| Temp1[63:0] ← SRC1[63:32] * SRC2[63:32] |
| Temp2[63:0] ← SRC1[95:64] * SRC2[95:64] |
| Temp3[63:0] ← SRC1[127:96] * SRC2[127:96] |
| DEST[31:0] ← Temp0[31:0] |
| DEST[63:32] ← Temp1[31:0] |
| DEST[95:64] ← Temp2[31:0] |
| DEST[127:96] ← Temp3[31:0] |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VPMULLD (VEX.256 encoded version)</strong></p> |
| <pre>Temp0[63:0] ← SRC1[31:0] * SRC2[31:0] |
| Temp1[63:0] ← SRC1[63:32] * SRC2[63:32] |
| Temp2[63:0] ← SRC1[95:64] * SRC2[95:64] |
| Temp3[63:0] ← SRC1[127:96] * SRC2[127:96] |
| Temp4[63:0] ← SRC1[159:128] * SRC2[159:128] |
| Temp5[63:0] ← SRC1[191:160] * SRC2[191:160] |
| Temp6[63:0] ← SRC1[223:192] * SRC2[223:192] |
| Temp7[63:0] ← SRC1[255:224] * SRC2[255:224]</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>(V)PMULLUD:</p> |
| <p> __m128i _mm_mullo_epi32(__m128i a, __m128i b);</p> |
| <p>VPMULLD:</p> |
| <p>__m256i _mm256_mullo_epi32(__m256i a, __m256i b);</p> |
| <h2>Flags Affected</h2> |
| <p>None.</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>None.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 4; additionally</p> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td>If VEX.L = 1.</td></tr></table></body></html> |