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 <title>PMULHUW—Multiply Packed Unsigned Integers and Store High Result </title></head>
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 <h1>PMULHUW—Multiply Packed Unsigned Integers and Store High Result</h1>
 <table>
 <tr>
 <th>Opcode/Instruction</th>
 <th>Op/En</th>
 <th>64/32 bit Mode Support</th>
 <th>CPUID Feature Flag</th>
 <th>Description</th></tr>
 <tr>
 <td>
 <p>0F E4 /<em>r</em><sup>1</sup></p>
 <p>PMULHUW <em>mm1</em>, <em>mm2/m64</em></p></td>
 <td>RM</td>
 <td>V/V</td>
 <td>SSE</td>
 <td>Multiply the packed unsigned word integers in <em>mm1</em> register and <em>mm2/m64</em>, and store the high 16 bits of the results in <em>mm1</em>.</td></tr>
 <tr>
 <td>
 <p>66 0F E4 /<em>r</em></p>
 <p>PMULHUW <em>xmm1</em>, <em>xmm2/m128</em></p></td>
 <td>RM</td>
 <td>V/V</td>
 <td>SSE2</td>
 <td>Multiply the packed unsigned word integers in <em>xmm1</em> and <em>xmm2/m128</em>, and store the high 16 bits of the results in <em>xmm1</em>.</td></tr>
 <tr>
 <td>
 <p>VEX.NDS.128.66.0F.WIG E4 /r</p>
 <p>VPMULHUW <em>xmm1, xmm2, xmm3/m128</em></p></td>
 <td>RVM</td>
 <td>V/V</td>
 <td>AVX</td>
 <td>Multiply the packed unsigned word integers in <em>xmm2</em> and <em>xmm3/m128</em>, and store the high 16 bits of the results in <em>xmm1</em>.</td></tr>
 <tr>
 <td>
 <p>VEX.NDS.256.66.0F.WIG E4 /r</p>
 <p>VPMULHUW <em>ymm1, ymm2, ymm3/m256</em></p></td>
 <td>RVM</td>
 <td>V/V</td>
 <td>AVX2</td>
 <td>Multiply the packed unsigned word integers in <em>ymm2</em> and <em>ymm3/m256</em>, and store the high 16 bits of the results in <em>ymm1</em>.</td></tr></table>
 <p>NOTES:</p>
 <p>1. See note in Section 2.4, “Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
 <h3>Instruction Operand Encoding</h3>
 <table>
 <tr>
 <td>Op/En</td>
 <td>Operand 1</td>
 <td>Operand 2</td>
 <td>Operand 3</td>
 <td>Operand 4</td></tr>
 <tr>
 <td>RM</td>
 <td>ModRM:reg (r, w)</td>
 <td>ModRM:r/m (r)</td>
 <td>NA</td>
 <td>NA</td></tr>
 <tr>
 <td>RVM</td>
 <td>ModRM:reg (w)</td>
 <td>VEX.vvvv (r)</td>
 <td>ModRM:r/m (r)</td>
 <td>NA</td></tr></table>
 <h2>Description</h2>
 <p>Performs a SIMD unsigned multiply of the packed unsigned word integers in the destination operand (first operand) and the source operand (second operand), and stores the high 16 bits of each 32-bit intermediate results in the destination operand. (Figure 4-8 shows this operation when using 64-bit operands.)</p>
 <p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
 <p>Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an MMX technology register.</p>
 <p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-tion register remain unchanged.</p>
 <p>VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.L must be 0, otherwise the instruction will #UD.</p>
 <p>VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.</p>
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 <h3>Figure 4-8.  PMULHUW and PMULHW Instruction Operation Using 64-bit Operands</h3>
 <h2>Operation</h2>
 <p><strong>PMULHUW (with 64-bit operands)</strong></p>
 <pre>    TEMP0[31:0] ←
                          DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *)
     TEMP1[31:0] ←
                          DEST[31:16] ∗ SRC[31:16];
     TEMP2[31:0] ←
                          DEST[47:32] ∗ SRC[47:32];
     TEMP3[31:0] ←
                          DEST[63:48] ∗ SRC[63:48];
     DEST[15:0] ←
                          TEMP0[31:16];
     DEST[31:16] ←
                          TEMP1[31:16];
     DEST[47:32] ←
                          TEMP2[31:16];
     DEST[63:48] ←
                          TEMP3[31:16];</pre>
 <p><strong>PMULHUW (with 128-bit operands)</strong></p>
 <pre>    TEMP0[31:0] ←
                          DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *)
     TEMP1[31:0] ←
                          DEST[31:16] ∗ SRC[31:16];
     TEMP2[31:0] ←
                          DEST[47:32] ∗ SRC[47:32];
     TEMP3[31:0] ←
                          DEST[63:48] ∗ SRC[63:48];
     TEMP4[31:0] ←
                          DEST[79:64] ∗ SRC[79:64];
     TEMP5[31:0] ←
                          DEST[95:80] ∗ SRC[95:80];
     TEMP6[31:0] ←
                          DEST[111:96] ∗ SRC[111:96];
     TEMP7[31:0] ←
                          DEST[127:112] ∗ SRC[127:112];
     DEST[15:0] ←
                          TEMP0[31:16];
     DEST[31:16] ←
                          TEMP1[31:16];
     DEST[47:32] ←
                          TEMP2[31:16];
     DEST[63:48] ←
                          TEMP3[31:16];
     DEST[79:64] ←
                          TEMP4[31:16];
     DEST[95:80] ←
                          TEMP5[31:16];
     DEST[111:96] ←  TEMP6[31:16];
     DEST[127:112] ← TEMP7[31:16];</pre>
 <p><strong>VPMULHUW (VEX.128 encoded version)</strong></p>
 <pre>TEMP0[31:0] ← SRC1[15:0] * SRC2[15:0]
 TEMP1[31:0] ← SRC1[31:16] * SRC2[31:16]
 TEMP2[31:0] ← SRC1[47:32] * SRC2[47:32]
 TEMP3[31:0] ← SRC1[63:48] * SRC2[63:48]
 TEMP4[31:0] ← SRC1[79:64] * SRC2[79:64]
 TEMP5[31:0] ← SRC1[95:80] * SRC2[95:80]
 TEMP6[31:0] ← SRC1[111:96] * SRC2[111:96]
 TEMP7[31:0] ← SRC1[127:112] * SRC2[127:112]
 DEST[15:0] ← TEMP0[31:16]
 DEST[31:16] ← TEMP1[31:16]
 DEST[47:32] ← TEMP2[31:16]
 DEST[63:48] ← TEMP3[31:16]
 DEST[79:64] ← TEMP4[31:16]
 DEST[95:80] ← TEMP5[31:16]
 DEST[111:96] ← TEMP6[31:16]
 DEST[127:112] ← TEMP7[31:16]
 DEST[VLMAX-1:128] ← 0</pre>
 <p><strong>PMULHUW (VEX.256 encoded version)</strong></p>
 <pre>TEMP0[31:0] ← SRC1[15:0] * SRC2[15:0]
 TEMP1[31:0] ← SRC1[31:16] * SRC2[31:16]
 TEMP2[31:0] ← SRC1[47:32] * SRC2[47:32]
 TEMP3[31:0] ← SRC1[63:48] * SRC2[63:48]
 TEMP4[31:0] ← SRC1[79:64] * SRC2[79:64]
 TEMP5[31:0] ← SRC1[95:80] * SRC2[95:80]
 TEMP6[31:0] ← SRC1[111:96] * SRC2[111:96]
 TEMP7[31:0] ← SRC1[127:112] * SRC2[127:112]
 TEMP8[31:0] ← SRC1[143:128] * SRC2[143:128]
 TEMP9[31:0] ← SRC1[159:144] * SRC2[159:144]
 TEMP10[31:0] ← SRC1[175:160] * SRC2[175:160]
 TEMP11[31:0] ← SRC1[191:176] * SRC2[191:176]
 TEMP12[31:0] ← SRC1[207:192] * SRC2[207:192]
 TEMP13[31:0] ← SRC1[223:208] * SRC2[223:208]
 TEMP14[31:0] ← SRC1[239:224] * SRC2[239:224]
 TEMP15[31:0] ← SRC1[255:240] * SRC2[255:240]
 DEST[15:0] ← TEMP0[31:16]
 DEST[31:16] ← TEMP1[31:16]
 DEST[47:32] ← TEMP2[31:16]
 DEST[63:48] ← TEMP3[31:16]
 DEST[79:64] ← TEMP4[31:16]
 DEST[95:80] ← TEMP5[31:16]
 DEST[111:96] ← TEMP6[31:16]
 DEST[127:112] ← TEMP7[31:16]
 DEST[143:128] ← TEMP8[31:16]
 DEST[159:144] ← TEMP9[31:16]
 DEST[175:160] ← TEMP10[31:16]
 DEST[191:176] ← TEMP11[31:16]
 DEST[207:192] ← TEMP12[31:16]
 DEST[223:208] ← TEMP13[31:16]
 DEST[239:224] ← TEMP14[31:16]
 DEST[255:240] ← TEMP15[31:16]</pre>
 <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
 <p>PMULHUW:</p>
 <p>__m64 _mm_mulhi_pu16(__m64 a, __m64 b)</p>
 <p>(V)PMULHUW:</p>
 <p>__m128i _mm_mulhi_epu16 ( __m128i a, __m128i b)</p>
 <p>VPMULHUW:</p>
 <p>__m256i _mm256_mulhi_epu16 ( __m256i a, __m256i b)</p>
 <h2>Flags Affected</h2>
 <p>None.</p>
 <h2>Numeric Exceptions</h2>
 <p>None.</p>
 <h2>Other Exceptions</h2>
 <p>See Exceptions Type 4; additionally</p>
 <table class="exception-table">
 <tr>
 <td>#UD</td>
 <td>If VEX.L = 1.</td></tr></table></body></html>
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	<title>PMULHUW—Multiply Packed Unsigned Integers and Store High Result </title></head>
	<body>
	<h1>PMULHUW—Multiply Packed Unsigned Integers and Store High Result</h1>
	<table>
	<tr>
	<th>Opcode/Instruction</th>
	<th>Op/En</th>
	<th>64/32 bit Mode Support</th>
	<th>CPUID Feature Flag</th>
	<th>Description</th></tr>
	<tr>
	<td>
	<p>0F E4 /<em>r</em><sup>1</sup></p>
	<p>PMULHUW <em>mm1</em>, <em>mm2/m64</em></p></td>
	<td>RM</td>
	<td>V/V</td>
	<td>SSE</td>
	<td>Multiply the packed unsigned word integers in <em>mm1</em> register and <em>mm2/m64</em>, and store the high 16 bits of the results in <em>mm1</em>.</td></tr>
	<tr>
	<td>
	<p>66 0F E4 /<em>r</em></p>
	<p>PMULHUW <em>xmm1</em>, <em>xmm2/m128</em></p></td>
	<td>RM</td>
	<td>V/V</td>
	<td>SSE2</td>
	<td>Multiply the packed unsigned word integers in <em>xmm1</em> and <em>xmm2/m128</em>, and store the high 16 bits of the results in <em>xmm1</em>.</td></tr>
	<tr>
	<td>
	<p>VEX.NDS.128.66.0F.WIG E4 /r</p>
	<p>VPMULHUW <em>xmm1, xmm2, xmm3/m128</em></p></td>
	<td>RVM</td>
	<td>V/V</td>
	<td>AVX</td>
	<td>Multiply the packed unsigned word integers in <em>xmm2</em> and <em>xmm3/m128</em>, and store the high 16 bits of the results in <em>xmm1</em>.</td></tr>
	<tr>
	<td>
	<p>VEX.NDS.256.66.0F.WIG E4 /r</p>
	<p>VPMULHUW <em>ymm1, ymm2, ymm3/m256</em></p></td>
	<td>RVM</td>
	<td>V/V</td>
	<td>AVX2</td>
	<td>Multiply the packed unsigned word integers in <em>ymm2</em> and <em>ymm3/m256</em>, and store the high 16 bits of the results in <em>ymm1</em>.</td></tr></table>
	<p>NOTES:</p>
	<p>1. See note in Section 2.4, “Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
	<h3>Instruction Operand Encoding</h3>
	<table>
	<tr>
	<td>Op/En</td>
	<td>Operand 1</td>
	<td>Operand 2</td>
	<td>Operand 3</td>
	<td>Operand 4</td></tr>
	<tr>
	<td>RM</td>
	<td>ModRM:reg (r, w)</td>
	<td>ModRM:r/m (r)</td>
	<td>NA</td>
	<td>NA</td></tr>
	<tr>
	<td>RVM</td>
	<td>ModRM:reg (w)</td>
	<td>VEX.vvvv (r)</td>
	<td>ModRM:r/m (r)</td>
	<td>NA</td></tr></table>
	<h2>Description</h2>
	<p>Performs a SIMD unsigned multiply of the packed unsigned word integers in the destination operand (first operand) and the source operand (second operand), and stores the high 16 bits of each 32-bit intermediate results in the destination operand. (Figure 4-8 shows this operation when using 64-bit operands.)</p>
	<p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
	<p>Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an MMX technology register.</p>
	<p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-tion register remain unchanged.</p>
	<p>VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.L must be 0, otherwise the instruction will #UD.</p>
	<p>VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.</p>
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	<h3>Figure 4-8. PMULHUW and PMULHW Instruction Operation Using 64-bit Operands</h3>
	<h2>Operation</h2>
	<p><strong>PMULHUW (with 64-bit operands)</strong></p>
	<pre> TEMP0[31:0] ←
	DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *)
	TEMP1[31:0] ←
	DEST[31:16] ∗ SRC[31:16];
	TEMP2[31:0] ←
	DEST[47:32] ∗ SRC[47:32];
	TEMP3[31:0] ←
	DEST[63:48] ∗ SRC[63:48];
	DEST[15:0] ←
	TEMP0[31:16];
	DEST[31:16] ←
	TEMP1[31:16];
	DEST[47:32] ←
	TEMP2[31:16];
	DEST[63:48] ←
	TEMP3[31:16];</pre>
	<p><strong>PMULHUW (with 128-bit operands)</strong></p>
	<pre> TEMP0[31:0] ←
	DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *)
	TEMP1[31:0] ←
	DEST[31:16] ∗ SRC[31:16];
	TEMP2[31:0] ←
	DEST[47:32] ∗ SRC[47:32];
	TEMP3[31:0] ←
	DEST[63:48] ∗ SRC[63:48];
	TEMP4[31:0] ←
	DEST[79:64] ∗ SRC[79:64];
	TEMP5[31:0] ←
	DEST[95:80] ∗ SRC[95:80];
	TEMP6[31:0] ←
	DEST[111:96] ∗ SRC[111:96];
	TEMP7[31:0] ←
	DEST[127:112] ∗ SRC[127:112];
	DEST[15:0] ←
	TEMP0[31:16];
	DEST[31:16] ←
	TEMP1[31:16];
	DEST[47:32] ←
	TEMP2[31:16];
	DEST[63:48] ←
	TEMP3[31:16];
	DEST[79:64] ←
	TEMP4[31:16];
	DEST[95:80] ←
	TEMP5[31:16];
	DEST[111:96] ← TEMP6[31:16];
	DEST[127:112] ← TEMP7[31:16];</pre>
	<p><strong>VPMULHUW (VEX.128 encoded version)</strong></p>
	<pre>TEMP0[31:0] ← SRC1[15:0] * SRC2[15:0]
	TEMP1[31:0] ← SRC1[31:16] * SRC2[31:16]
	TEMP2[31:0] ← SRC1[47:32] * SRC2[47:32]
	TEMP3[31:0] ← SRC1[63:48] * SRC2[63:48]
	TEMP4[31:0] ← SRC1[79:64] * SRC2[79:64]
	TEMP5[31:0] ← SRC1[95:80] * SRC2[95:80]
	TEMP6[31:0] ← SRC1[111:96] * SRC2[111:96]
	TEMP7[31:0] ← SRC1[127:112] * SRC2[127:112]
	DEST[15:0] ← TEMP0[31:16]
	DEST[31:16] ← TEMP1[31:16]
	DEST[47:32] ← TEMP2[31:16]
	DEST[63:48] ← TEMP3[31:16]
	DEST[79:64] ← TEMP4[31:16]
	DEST[95:80] ← TEMP5[31:16]
	DEST[111:96] ← TEMP6[31:16]
	DEST[127:112] ← TEMP7[31:16]
	DEST[VLMAX-1:128] ← 0</pre>
	<p><strong>PMULHUW (VEX.256 encoded version)</strong></p>
	<pre>TEMP0[31:0] ← SRC1[15:0] * SRC2[15:0]
	TEMP1[31:0] ← SRC1[31:16] * SRC2[31:16]
	TEMP2[31:0] ← SRC1[47:32] * SRC2[47:32]
	TEMP3[31:0] ← SRC1[63:48] * SRC2[63:48]
	TEMP4[31:0] ← SRC1[79:64] * SRC2[79:64]
	TEMP5[31:0] ← SRC1[95:80] * SRC2[95:80]
	TEMP6[31:0] ← SRC1[111:96] * SRC2[111:96]
	TEMP7[31:0] ← SRC1[127:112] * SRC2[127:112]
	TEMP8[31:0] ← SRC1[143:128] * SRC2[143:128]
	TEMP9[31:0] ← SRC1[159:144] * SRC2[159:144]
	TEMP10[31:0] ← SRC1[175:160] * SRC2[175:160]
	TEMP11[31:0] ← SRC1[191:176] * SRC2[191:176]
	TEMP12[31:0] ← SRC1[207:192] * SRC2[207:192]
	TEMP13[31:0] ← SRC1[223:208] * SRC2[223:208]
	TEMP14[31:0] ← SRC1[239:224] * SRC2[239:224]
	TEMP15[31:0] ← SRC1[255:240] * SRC2[255:240]
	DEST[15:0] ← TEMP0[31:16]
	DEST[31:16] ← TEMP1[31:16]
	DEST[47:32] ← TEMP2[31:16]
	DEST[63:48] ← TEMP3[31:16]
	DEST[79:64] ← TEMP4[31:16]
	DEST[95:80] ← TEMP5[31:16]
	DEST[111:96] ← TEMP6[31:16]
	DEST[127:112] ← TEMP7[31:16]
	DEST[143:128] ← TEMP8[31:16]
	DEST[159:144] ← TEMP9[31:16]
	DEST[175:160] ← TEMP10[31:16]
	DEST[191:176] ← TEMP11[31:16]
	DEST[207:192] ← TEMP12[31:16]
	DEST[223:208] ← TEMP13[31:16]
	DEST[239:224] ← TEMP14[31:16]
	DEST[255:240] ← TEMP15[31:16]</pre>
	<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
	<p>PMULHUW:</p>
	<p>__m64 _mm_mulhi_pu16(__m64 a, __m64 b)</p>
	<p>(V)PMULHUW:</p>
	<p>__m128i _mm_mulhi_epu16 ( __m128i a, __m128i b)</p>
	<p>VPMULHUW:</p>
	<p>__m256i _mm256_mulhi_epu16 ( __m256i a, __m256i b)</p>
	<h2>Flags Affected</h2>
	<p>None.</p>
	<h2>Numeric Exceptions</h2>
	<p>None.</p>
	<h2>Other Exceptions</h2>
	<p>See Exceptions Type 4; additionally</p>
	<table class="exception-table">
	<tr>
	<td>#UD</td>
	<td>If VEX.L = 1.</td></tr></table></body></html>