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| <title>PMINSW—Minimum of Packed Signed Word Integers </title></head> |
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| <h1>PMINSW—Minimum of Packed Signed Word Integers</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 bit Mode Support</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>0F EA /<em>r</em><sup>1</sup></p> |
| <p>PMINSW <em>mm1, mm2/m64</em></p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE</td> |
| <td>Compare signed word integers in <em>mm2/m64 </em>and <em>mm1</em> and return minimum values.</td></tr> |
| <tr> |
| <td> |
| <p>66 0F EA /<em>r</em></p> |
| <p>PMINSW <em>xmm1</em>, <em>xmm2/m128</em></p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE2</td> |
| <td>Compare signed word integers in <em>xmm2/m128 </em>and <em>xmm1</em> and return minimum values.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.NDS.128.66.0F.WIG EA /r</p> |
| <p>VPMINSW <em>xmm1, xmm2, xmm3/m128</em></p></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Compare packed signed word integers in <em>xmm3/m128</em> and <em>xmm2</em> and return packed minimum values in <em>xmm1</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.NDS.256.66.0F.WIG EA /r</p> |
| <p>VPMINSW <em>ymm1, ymm2, ymm3/m256</em></p></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX2</td> |
| <td>Compare packed signed word integers in <em>ymm3/m256</em> and <em>ymm2</em> and return packed minimum values in <em>ymm1</em>.</td></tr></table> |
| <p>NOTES:</p> |
| <p>1. See note in Section 2.4, “Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RVM</td> |
| <td>ModRM:reg (w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Performs a SIMD compare of the packed signed word integers in the destination operand (first operand) and the source operand (second operand), and returns the minimum value for each pair of word integers to the destination operand.</p> |
| <p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p> |
| <p>Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand can be an MMX technology register.</p> |
| <p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-tion register remain unchanged.</p> |
| <p>VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p> |
| <p>VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.</p> |
| <p>Note: VEX.L must be 0, otherwise the instruction will #UD.</p> |
| <h2>Operation</h2> |
| <p><strong>PMINSW (64-bit operands)</strong></p> |
| <pre> IF DEST[15:0] < SRC[15:0] THEN |
| DEST[15:0] ← DEST[15:0]; |
| ELSE |
| DEST[15:0] ← SRC[15:0]; FI; |
| (* Repeat operation for 2nd and 3rd words in source and destination operands *) |
| IF DEST[63:48] < SRC[63:48] THEN |
| DEST[63:48] ← DEST[63:48]; |
| ELSE |
| DEST[63:48] ← SRC[63:48]; FI;</pre> |
| <p><strong>PMINSW (128-bit operands)</strong></p> |
| <pre> IF DEST[15:0] < SRC[15:0] THEN |
| DEST[15:0] ← DEST[15:0]; |
| ELSE |
| DEST[15:0] ← SRC[15:0]; FI; |
| (* Repeat operation for 2nd through 7th words in source and destination operands *) |
| IF DEST[127:112] < SRC/m64[127:112] THEN |
| DEST[127:112] ← DEST[127:112]; |
| ELSE |
| DEST[127:112] ← SRC[127:112]; FI;</pre> |
| <p><strong>VPMINSW (VEX.128 encoded version)</strong></p> |
| <pre> IF SRC1[15:0] < SRC2[15:0] THEN |
| DEST[15:0] ← SRC1[15:0]; |
| ELSE |
| DEST[15:0] ← SRC2[15:0]; FI; |
| (* Repeat operation for 2nd through 7th words in source and destination operands *) |
| IF SRC1[127:112] < SRC2[127:112] THEN |
| DEST[127:112] ← SRC1[127:112]; |
| ELSE |
| DEST[127:112] ← SRC2[127:112]; FI; |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VPMINSW (VEX.256 encoded version)</strong></p> |
| <pre> IF SRC1[15:0] < SRC2[15:0] THEN |
| DEST[15:0] ← SRC1[15:0]; |
| ELSE |
| DEST[15:0] ← SRC2[15:0]; FI; |
| (* Repeat operation for 2nd through 15th words in source and destination operands *) |
| IF SRC1[255:240] < SRC2[255:240] THEN |
| DEST[255:240] ← SRC1[255:240]; |
| ELSE |
| DEST[255:240] ← SRC2[255:240]; FI;</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>PMINSW:</p> |
| <p>__m64 _mm_min_pi16 (__m64 a, __m64 b)</p> |
| <p>(V)PMINSW:</p> |
| <p>__m128i _mm_min_epi16 ( __m128i a, __m128i b)</p> |
| <p>VPMINSW:</p> |
| <p>__m256i _mm256_min_epi16 ( __m256i a, __m256i b)</p> |
| <h2>Flags Affected</h2> |
| <p>None.</p> |
| <h2>Numeric Exceptions</h2> |
| <p>None.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 4; additionally</p> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td>If VEX.L = 1.</td></tr> |
| <tr> |
| <td>#MF</td> |
| <td>(64-bit operations only) If there is a pending x87 FPU exception.</td></tr></table></body></html> |