| <!DOCTYPE html> |
| |
| <html> |
| <head> |
| <meta charset="UTF-8"> |
| <link href="style.css" type="text/css" rel="stylesheet"> |
| <title>PMAXSD — Maximum of Packed Signed Dword Integers </title></head> |
| <body> |
| <h1>PMAXSD — Maximum of Packed Signed Dword Integers</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 bit Mode Support</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td>66 0F 38 3D /r PMAXSD <em>xmm1, xmm2/m128</em></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE4_1</td> |
| <td>Compare packed signed dword integers in <em>xmm1</em> and <em>xmm2/m128 </em>and store packed maximum values in <em>xmm1</em>.</td></tr> |
| <tr> |
| <td>VEX.NDS.128.66.0F38.WIG 3D /r VPMAXSD <em>xmm1, xmm2, xmm3/m128</em></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Compare packed signed dword integers in <em>xmm2</em> and <em>xmm3/m128 </em>and store packed maximum values in <em>xmm1</em>.</td></tr> |
| <tr> |
| <td>VEX.NDS.256.66.0F38.WIG 3D /r VPMAXSD <em>ymm1, ymm2, ymm3/m256</em></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX2</td> |
| <td>Compare packed signed dword integers in <em>ymm2</em> and <em>ymm3/m128</em> and store packed maximum values in <em>ymm1</em>.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RVM</td> |
| <td>ModRM:reg (w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Compares packed signed dword integers in the destination operand (first operand) and the source operand (second operand), and returns the maximum for each packed value in the destination operand.</p> |
| <p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-tion register remain unchanged.</p> |
| <p>VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p> |
| <p>VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.</p> |
| <p>Note: VEX.L must be 0, otherwise the instruction will #UD.</p> |
| <h2>Operation</h2> |
| <pre>IF (DEST[31:0] > SRC[31:0]) |
| THEN DEST[31:0] ← DEST[31:0]; |
| ELSE DEST[31:0] ← SRC[31:0]; FI; |
| IF (DEST[63:32] > SRC[63:32]) |
| THEN DEST[63:32] ← DEST[63:32]; |
| ELSE DEST[63:32] ← SRC[63:32]; FI; |
| IF (DEST[95:64] > SRC[95:64]) |
| THEN DEST[95:64] ← DEST[95:64]; |
| ELSE DEST[95:64] ← SRC[95:64]; FI; |
| IF (DEST[127:96] > SRC[127:96]) |
| THEN DEST[127:96] ← DEST[127:96]; |
| ELSE DEST[127:96] ← SRC[127:96]; FI;</pre> |
| <p><strong>VPMAXSD (VEX.128 encoded version)</strong></p> |
| <pre> IF SRC1[31:0] > SRC2[31:0] THEN |
| DEST[31:0] ← SRC1[31:0]; |
| ELSE |
| DEST[31:0] ← SRC2[31:0]; FI; |
| (* Repeat operation for 2nd through 3rd dwords in source and destination operands *) |
| IF SRC1[127:95] > SRC2[127:95] THEN |
| DEST[127:95] ← SRC1[127:95]; |
| ELSE |
| DEST[127:95] ← SRC2[127:95]; FI; |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VPMAXSD (VEX.256 encoded version)</strong></p> |
| <pre> IF SRC1[31:0] > SRC2[31:0] THEN |
| DEST[31:0] ← SRC1[31:0]; |
| ELSE |
| DEST[31:0] ← SRC2[31:0]; FI; |
| (* Repeat operation for 2nd through 7th dwords in source and destination operands *) |
| IF SRC1[255:224] > SRC2[255:224] THEN |
| DEST[255:224] ← SRC1[255:224]; |
| ELSE |
| DEST[255:224] ← SRC2[255:224]; FI;</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>PMAXSD:</p> |
| <p> __m128i _mm_max_epi32 ( __m128i a, __m128i b);</p> |
| <p>VPMAXSD:</p> |
| <p>__m256i _mm256_max_epi32 ( __m256i a, __m256i b);</p> |
| <h2>Flags Affected</h2> |
| <p>None.</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>None.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 4; additionally</p> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td>If VEX.L = 1.</td></tr></table></body></html> |