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 <title>PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes </title></head>
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 <h1>PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes</h1>
 <table>
 <tr>
 <th>Opcode/Instruction</th>
 <th>Op/En</th>
 <th>64/32 bit Mode Support</th>
 <th>CPUID Feature Flag</th>
 <th>Description</th></tr>
 <tr>
 <td>
 <p>0F 38 04 /r<sup>1</sup></p>
 <p>PMADDUBSW <em>mm1, mm2/m64</em></p></td>
 <td>RM</td>
 <td>V/V</td>
 <td>SSSE3</td>
 <td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to <em>mm1</em>.</td></tr>
 <tr>
 <td>
 <p>66 0F 38 04 /r</p>
 <p>PMADDUBSW <em>xmm1, xmm2/m128</em></p></td>
 <td>RM</td>
 <td>V/V</td>
 <td>SSSE3</td>
 <td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to <em>xmm1</em>.</td></tr>
 <tr>
 <td>
 <p>VEX.NDS.128.66.0F38.WIG 04 /r</p>
 <p>VPMADDUBSW <em>xmm1, xmm2, xmm3/m128</em></p></td>
 <td>RVM</td>
 <td>V/V</td>
 <td>AVX</td>
 <td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to <em>xmm1</em>.</td></tr>
 <tr>
 <td>
 <p>VEX.NDS.256.66.0F38.WIG 04 /r</p>
 <p>VPMADDUBSW <em>ymm1, ymm2, ymm3/m256</em></p></td>
 <td>RVM</td>
 <td>V/V</td>
 <td>AVX2</td>
 <td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to <em>ymm1.</em></td></tr></table>
 <p>NOTES:</p>
 <p>1. See note in Section 2.4, “Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
 <h3>Instruction Operand Encoding</h3>
 <table>
 <tr>
 <td>Op/En</td>
 <td>Operand 1</td>
 <td>Operand 2</td>
 <td>Operand 3</td>
 <td>Operand 4</td></tr>
 <tr>
 <td>RM</td>
 <td>ModRM:reg (r, w)</td>
 <td>ModRM:r/m (r)</td>
 <td>NA</td>
 <td>NA</td></tr>
 <tr>
 <td>RVM</td>
 <td>ModRM:reg (w)</td>
 <td>VEX.vvvv (r)</td>
 <td>ModRM:r/m (r)</td>
 <td>NA</td></tr></table>
 <h2>Description</h2>
 <p>(V)PMADDUBSW multiplies vertically each unsigned byte of the destination operand (first operand) with the corre-sponding signed byte of the source operand (second operand), producing intermediate signed 16-bit integers. Each adjacent pair of signed words is added and the saturated result is packed to the destination operand. For example, the lowest-order bytes (bits 7-0) in the source and destination operands are multiplied and the intermediate signed word result is added with the corresponding intermediate result from the 2nd lowest-order bytes (bits 15-8) of the operands; the sign-saturated result is stored in the lowest word of the destination register (15-0). The same oper-ation is performed on the other pairs of adjacent bytes. Both operands can be MMX register or XMM registers. When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.</p>
 <p>In 64-bit mode, use the REX prefix to access additional registers.</p>
 <p>128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p>
 <p>VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p>
 <p>VEX.256 encoded version: The first source and destination operands are YMM registers. The second source operand can be an YMM register or a 256-bit memory location.</p>
 <p>Note: VEX.L must be 0, otherwise the instruction will #UD.</p>
 <h2>Operation</h2>
 <p><strong>PMADDUBSW (with 64 bit operands)</strong></p>
 <pre>    DEST[15-0] = SaturateToSignedWord(SRC[15-8]*DEST[15-8]+SRC[7-0]*DEST[7-0]);
     DEST[31-16] = SaturateToSignedWord(SRC[31-24]*DEST[31-24]+SRC[23-16]*DEST[23-16]);
     DEST[47-32] = SaturateToSignedWord(SRC[47-40]*DEST[47-40]+SRC[39-32]*DEST[39-32]);
     DEST[63-48] = SaturateToSignedWord(SRC[63-56]*DEST[63-56]+SRC[55-48]*DEST[55-48]);</pre>
 <p><strong>PMADDUBSW (with 128 bit operands)</strong></p>
 <pre>    DEST[15-0] = SaturateToSignedWord(SRC[15-8]* DEST[15-8]+SRC[7-0]*DEST[7-0]);
     // Repeat operation for 2nd through 7th word
     SRC1/DEST[127-112] = SaturateToSignedWord(SRC[127-120]*DEST[127-120]+ SRC[119-112]* DEST[119-112]);</pre>
 <p><strong>VPMADDUBSW (VEX.128 encoded version)</strong></p>
 <pre>DEST[15:0] ← SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
 // Repeat operation for 2nd through 7th word
 DEST[127:112] ← SaturateToSignedWord(SRC2[127:120]*SRC1[127:120]+ SRC2[119:112]* SRC1[119:112])
 DEST[VLMAX-1:128] ← 0</pre>
 <p><strong>VPMADDUBSW (VEX.256 encoded version)</strong></p>
 <pre>DEST[15:0] ← SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
 // Repeat operation for 2nd through 15th word
 DEST[255:240] ← SaturateToSignedWord(SRC2[255:248]*SRC1[255:248]+ SRC2[247:240]* SRC1[247:240])</pre>
 <h2>Intel C/C++ Compiler Intrinsic Equivalents</h2>
 <p>PMADDUBSW:</p>
 <p> __m64 _mm_maddubs_pi16 (__m64 a, __m64 b)</p>
 <p>(V)PMADDUBSW:</p>
 <p> __m128i _mm_maddubs_epi16 (__m128i a, __m128i b)</p>
 <p>VPMADDUBSW:</p>
 <p>__m256i _mm256_maddubs_epi16 (__m256i a, __m256i b)</p>
 <h2>SIMD Floating-Point Exceptions</h2>
 <p>None.</p>
 <h2>Other Exceptions</h2>
 <p>See Exceptions Type 4; additionally</p>
 <table class="exception-table">
 <tr>
 <td>#UD</td>
 <td>If VEX.L = 1.</td></tr></table></body></html>
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	<html>
	<head>
	<meta charset="UTF-8">
	<link href="style.css" type="text/css" rel="stylesheet">
	<title>PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes </title></head>
	<body>
	<h1>PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes</h1>
	<table>
	<tr>
	<th>Opcode/Instruction</th>
	<th>Op/En</th>
	<th>64/32 bit Mode Support</th>
	<th>CPUID Feature Flag</th>
	<th>Description</th></tr>
	<tr>
	<td>
	<p>0F 38 04 /r<sup>1</sup></p>
	<p>PMADDUBSW <em>mm1, mm2/m64</em></p></td>
	<td>RM</td>
	<td>V/V</td>
	<td>SSSE3</td>
	<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to <em>mm1</em>.</td></tr>
	<tr>
	<td>
	<p>66 0F 38 04 /r</p>
	<p>PMADDUBSW <em>xmm1, xmm2/m128</em></p></td>
	<td>RM</td>
	<td>V/V</td>
	<td>SSSE3</td>
	<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to <em>xmm1</em>.</td></tr>
	<tr>
	<td>
	<p>VEX.NDS.128.66.0F38.WIG 04 /r</p>
	<p>VPMADDUBSW <em>xmm1, xmm2, xmm3/m128</em></p></td>
	<td>RVM</td>
	<td>V/V</td>
	<td>AVX</td>
	<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to <em>xmm1</em>.</td></tr>
	<tr>
	<td>
	<p>VEX.NDS.256.66.0F38.WIG 04 /r</p>
	<p>VPMADDUBSW <em>ymm1, ymm2, ymm3/m256</em></p></td>
	<td>RVM</td>
	<td>V/V</td>
	<td>AVX2</td>
	<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to <em>ymm1.</em></td></tr></table>
	<p>NOTES:</p>
	<p>1. See note in Section 2.4, “Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
	<h3>Instruction Operand Encoding</h3>
	<table>
	<tr>
	<td>Op/En</td>
	<td>Operand 1</td>
	<td>Operand 2</td>
	<td>Operand 3</td>
	<td>Operand 4</td></tr>
	<tr>
	<td>RM</td>
	<td>ModRM:reg (r, w)</td>
	<td>ModRM:r/m (r)</td>
	<td>NA</td>
	<td>NA</td></tr>
	<tr>
	<td>RVM</td>
	<td>ModRM:reg (w)</td>
	<td>VEX.vvvv (r)</td>
	<td>ModRM:r/m (r)</td>
	<td>NA</td></tr></table>
	<h2>Description</h2>
	<p>(V)PMADDUBSW multiplies vertically each unsigned byte of the destination operand (first operand) with the corre-sponding signed byte of the source operand (second operand), producing intermediate signed 16-bit integers. Each adjacent pair of signed words is added and the saturated result is packed to the destination operand. For example, the lowest-order bytes (bits 7-0) in the source and destination operands are multiplied and the intermediate signed word result is added with the corresponding intermediate result from the 2nd lowest-order bytes (bits 15-8) of the operands; the sign-saturated result is stored in the lowest word of the destination register (15-0). The same oper-ation is performed on the other pairs of adjacent bytes. Both operands can be MMX register or XMM registers. When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.</p>
	<p>In 64-bit mode, use the REX prefix to access additional registers.</p>
	<p>128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p>
	<p>VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p>
	<p>VEX.256 encoded version: The first source and destination operands are YMM registers. The second source operand can be an YMM register or a 256-bit memory location.</p>
	<p>Note: VEX.L must be 0, otherwise the instruction will #UD.</p>
	<h2>Operation</h2>
	<p><strong>PMADDUBSW (with 64 bit operands)</strong></p>
	<pre> DEST[15-0] = SaturateToSignedWord(SRC[15-8]DEST[15-8]+SRC[7-0]DEST[7-0]);
	DEST[31-16] = SaturateToSignedWord(SRC[31-24]DEST[31-24]+SRC[23-16]DEST[23-16]);
	DEST[47-32] = SaturateToSignedWord(SRC[47-40]DEST[47-40]+SRC[39-32]DEST[39-32]);
	DEST[63-48] = SaturateToSignedWord(SRC[63-56]DEST[63-56]+SRC[55-48]DEST[55-48]);</pre>
	<p><strong>PMADDUBSW (with 128 bit operands)</strong></p>
	<pre> DEST[15-0] = SaturateToSignedWord(SRC[15-8]* DEST[15-8]+SRC[7-0]*DEST[7-0]);
	// Repeat operation for 2nd through 7th word
	SRC1/DEST[127-112] = SaturateToSignedWord(SRC[127-120]DEST[127-120]+ SRC[119-112] DEST[119-112]);</pre>
	<p><strong>VPMADDUBSW (VEX.128 encoded version)</strong></p>
	<pre>DEST[15:0] ← SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
	// Repeat operation for 2nd through 7th word
	DEST[127:112] ← SaturateToSignedWord(SRC2[127:120]SRC1[127:120]+ SRC2[119:112] SRC1[119:112])
	DEST[VLMAX-1:128] ← 0</pre>
	<p><strong>VPMADDUBSW (VEX.256 encoded version)</strong></p>
	<pre>DEST[15:0] ← SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
	// Repeat operation for 2nd through 15th word
	DEST[255:240] ← SaturateToSignedWord(SRC2[255:248]SRC1[255:248]+ SRC2[247:240] SRC1[247:240])</pre>
	<h2>Intel C/C++ Compiler Intrinsic Equivalents</h2>
	<p>PMADDUBSW:</p>
	<p> __m64 _mm_maddubs_pi16 (__m64 a, __m64 b)</p>
	<p>(V)PMADDUBSW:</p>
	<p> __m128i _mm_maddubs_epi16 (__m128i a, __m128i b)</p>
	<p>VPMADDUBSW:</p>
	<p>__m256i _mm256_maddubs_epi16 (__m256i a, __m256i b)</p>
	<h2>SIMD Floating-Point Exceptions</h2>
	<p>None.</p>
	<h2>Other Exceptions</h2>
	<p>See Exceptions Type 4; additionally</p>
	<table class="exception-table">
	<tr>
	<td>#UD</td>
	<td>If VEX.L = 1.</td></tr></table></body></html>