| <!DOCTYPE html> |
| |
| <html> |
| <head> |
| <meta charset="UTF-8"> |
| <link href="style.css" type="text/css" rel="stylesheet"> |
| <title>PCMPEQQ — Compare Packed Qword Data for Equal </title></head> |
| <body> |
| <h1>PCMPEQQ — Compare Packed Qword Data for Equal</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32 bit Mode Support</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td>66 0F 38 29 /r PCMPEQQ <em>xmm1, xmm2/m128</em></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE4_1</td> |
| <td>Compare packed qwords in <em>xmm2/m128</em> and <em>xmm1</em> for equality.</td></tr> |
| <tr> |
| <td>VEX.NDS.128.66.0F38.WIG 29 /r VPCMPEQQ <em>xmm1, xmm2, xmm3/m128</em></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Compare packed quadwords in <em>xmm3/m128 </em>and <em>xmm2 </em>for equality.</td></tr> |
| <tr> |
| <td>VEX.NDS.256.66.0F38.WIG 29 /r VPCMPEQQ <em>ymm1, ymm2, ymm3 /m256</em></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX2</td> |
| <td>Compare packed quadwords in <em>ymm3/m256 </em>and <em>ymm2</em> for equality.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RVM</td> |
| <td>ModRM:reg (w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Performs an SIMD compare for equality of the packed quadwords in the destination operand (first operand) and the source operand (second operand). If a pair of data elements is equal, the corresponding data element in the desti-nation is set to all 1s; otherwise, it is set to 0s.</p> |
| <p>128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p> |
| <p>VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register are zeroed.</p> |
| <p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p> |
| <p>Note: VEX.L must be 0, otherwise the instruction will #UD.</p> |
| <h2>Operation</h2> |
| <pre>IF (DEST[63:0] = SRC[63:0]) |
| THEN DEST[63:0] ← FFFFFFFFFFFFFFFFH; |
| ELSE DEST[63:0] ← 0; FI; |
| IF (DEST[127:64] = SRC[127:64]) |
| THEN DEST[127:64] ← FFFFFFFFFFFFFFFFH; |
| ELSE DEST[127:64] ← 0; FI;</pre> |
| <p><strong>VPCMPEQQ (VEX.128 encoded version)</strong></p> |
| <pre>DEST[127:0] ←COMPARE_QWORDS_EQUAL(SRC1,SRC2) |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VPCMPEQQ (VEX.256 encoded version)</strong></p> |
| <pre>DEST[127:0] ←COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0]) |
| DEST[255:128] ←COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>(V)PCMPEQQ:</p> |
| <p>__m128i _mm_cmpeq_epi64(__m128i a, __m128i b);</p> |
| <p>VPCMPEQQ:</p> |
| <p>__m256i _mm256_cmpeq_epi64( __m256i a, __m256i b);</p> |
| <h2>Flags Affected</h2> |
| <p>None.</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>None.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 4; additionally</p> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td>If VEX.L = 1.</td></tr></table></body></html> |