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| <title>PAUSE—Spin Loop Hint </title></head> |
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| <h1>PAUSE—Spin Loop Hint</h1> |
| <table> |
| <tr> |
| <th>Opcode</th> |
| <th>Instruction</th> |
| <th>Op/En</th> |
| <th>64-Bit Mode</th> |
| <th>Compat/Leg Mode</th> |
| <th>Description</th></tr> |
| <tr> |
| <td>F3 90</td> |
| <td>PAUSE</td> |
| <td>NP</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Gives hint to processor that improves performance of spin-wait loops.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>NP</td> |
| <td>NA</td> |
| <td>NA</td> |
| <td>NA</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Improves the performance of spin-wait loops. When executing a “spin-wait loop,” processors will suffer a severe performance penalty when exiting the loop because it detects a possible memory order violation. The PAUSE instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses this hint to avoid the memory order violation in most situations, which greatly improves processor performance. For this reason, it is recommended that a PAUSE instruction be placed in all spin-wait loops.</p> |
| <p>An additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a spin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of power while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-wait loop greatly reduces the processor’s power consumption.</p> |
| <p>This instruction was introduced in the Pentium 4 processors, but is backward compatible with all IA-32 processors. In earlier IA-32 processors, the PAUSE instruction operates like a NOP instruction. The Pentium 4 and Intel Xeon processors implement the PAUSE instruction as a delay. The delay is finite and can be zero for some processors. This instruction does not change the architectural state of the processor (that is, it performs essentially a delaying no-op operation).</p> |
| <p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p> |
| <h2>Operation</h2> |
| <pre>Execute_Next_Instruction(DELAY);</pre> |
| <h2>Numeric Exceptions</h2> |
| <p>None.</p> |
| <h2>Exceptions (All Operating Modes)</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td>If the LOCK prefix is used.</td></tr></table></body></html> |