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| <title>MULSS—Multiply Scalar Single-Precision Floating-Point Values </title></head> |
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| <h1>MULSS—Multiply Scalar Single-Precision Floating-Point Values</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32-bit Mode</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>F3 0F 59 /<em>r</em></p> |
| <p>MULSS <em>xmm1</em>, <em>xmm2/m32</em></p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE</td> |
| <td>Multiply the low single-precision floating-point value in <em>xmm2/mem</em> by the low single-precision floating-point value in <em>xmm1</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.NDS.LIG.F3.0F.WIG 59 /r</p> |
| <p>VMULSS <em>xmm1,xmm2, xmm3/m32</em></p></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Multiply the low single-precision floating-point value in <em>xmm3/mem</em> by the low single-precision floating-point value in <em>xmm2</em>.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RVM</td> |
| <td>ModRM:reg (w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Multiplies the low single-precision floating-point value from the source operand (second operand) by the low single-precision floating-point value in the destination operand (first operand), and stores the single-precision floating-point result in the destination operand. The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1</em>, for an illustration of a scalar single-precision floating-point operation.</p> |
| <p>In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).</p> |
| <p>128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-1:32) of the corresponding YMM destination register remain unchanged.</p> |
| <p>VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p> |
| <h2>Operation</h2> |
| <p><strong>MULSS (128-bit Legacy SSE version)</strong></p> |
| <pre>DEST[31:0] ← DEST[31:0] * SRC[31:0] |
| DEST[VLMAX-1:32] (Unmodified)</pre> |
| <p><strong>VMULSS (VEX.128 encoded version)</strong></p> |
| <pre>DEST[31:0] ← SRC1[31:0] * SRC2[31:0] |
| DEST[127:32] ← SRC1[127:32] |
| DEST[VLMAX-1:128] ← 0</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>MULSS:</p> |
| <p>__m128 _mm_mul_ss(__m128 a, __m128 b)</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>Overflow, Underflow, Invalid, Precision, Denormal.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 3</p></body></html> |