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<title>MOVSD—Move Scalar Double-Precision Floating-Point Value </title></head>
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<h1>MOVSD—Move Scalar Double-Precision Floating-Point Value</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32-bit Mode</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>F2 0F 10 /<em>r</em></p>
<p>MOVSD <em>xmm1</em>, <em>xmm2/m64</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move scalar double-precision floating-point value from <em>xmm2/m64</em> to <em>xmm1</em> register.</td></tr>
<tr>
<td>
<p>VEX.NDS.LIG.F2.0F.WIG 10 /r</p>
<p>VMOVSD <em>xmm1, xmm2, xmm3</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Merge scalar double-precision floating-point value from <em>xmm2</em> and <em>xmm3</em> to <em>xmm1 </em>register.</td></tr>
<tr>
<td>
<p>VEX.LIG.F2.0F.WIG 10 /r</p>
<p>VMOVSD <em>xmm1, m64</em></p></td>
<td>XM</td>
<td>V/V</td>
<td>AVX</td>
<td>Load scalar double-precision floating-point value from <em>m64</em> to <em>xmm1</em> register.</td></tr>
<tr>
<td>
<p>F2 0F 11 /<em>r</em></p>
<p>MOVSD <em>xmm2/m64</em>, <em>xmm1</em></p></td>
<td>MR</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move scalar double-precision floating-point value from <em>xmm1</em> register to <em>xmm2/m64</em>.</td></tr>
<tr>
<td>
<p>VEX.NDS.LIG.F2.0F.WIG 11 /r</p>
<p>VMOVSD <em>xmm1, xmm2, xmm3</em></p></td>
<td>MVR</td>
<td>V/V</td>
<td>AVX</td>
<td>Merge scalar double-precision floating-point value from <em>xmm2</em> and <em>xmm3</em> registers to <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.LIG.F2.0F.WIG 11 /r</p>
<p>VMOVSD <em>m64, xmm1</em></p></td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Move scalar double-precision floating-point value from <em>xmm1</em> register to <em>m64</em>.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>XM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>MVR</td>
<td>ModRM:r/m (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:reg (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>MOVSD moves a scalar double-precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be XMM registers or 64-bit memory locations. This instruction can be used to move a double-precision floating-point value to and from the low quad-word of an XMM register and a 64-bit memory location, or to move a double-precision floating-point value between the low quadwords of two XMM registers. The instruction cannot be used to transfer data between memory loca-tions.</p>
<p>For non-VEX encoded instruction syntax and when the source and destination operands are XMM registers, the high quadword of the destination operand remains unchanged. When the source operand is a memory location and destination operand is an XMM registers, the high quadword of the destination operand is cleared to all 0s.</p>
<p>In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>Note: For the “VMOVSD m64, xmm1” (memory store form) instruction version, VEX.vvvv is reserved and must be 1111b, otherwise instruction will #UD.</p>
<p>Note: For the “VMOVSD xmm1, m64” (memory load form) instruction version, VEX.vvvv is reserved and must be 1111b otherwise instruction will #UD.</p>
<p>VEX encoded instruction syntax supports two source operands and a destination operand if ModR/M.mod field is 11B. VEX.vvvv is used to encode the first source operand (the second operand). The low 128 bits of the destination operand stores the result of merging the low quadword of the second source operand with the quad word in bits 127:64 of the first source operand. The upper bits of the destination operand are cleared.</p>
<h2>Operation</h2>
<p><strong>MOVSD (128-bit Legacy SSE version: MOVSD XMM1, XMM2)</strong></p>
<pre>DEST[63:0] ← SRC[63:0]
DEST[VLMAX-1:64] (Unmodified)</pre>
<p><strong>MOVSD/VMOVSD (128-bit versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)</strong></p>
<pre>DEST[63:0] ← SRC[63:0]</pre>
<p><strong>MOVSD (128-bit Legacy SSE version: MOVSD XMM1, m64)</strong></p>
<pre>DEST[63:0] ← SRC[63:0]
DEST[127:64] ← 0
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>VMOVSD (VEX.NDS.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)</strong></p>
<pre>DEST[63:0] ← SRC2[63:0]
DEST[127:64] ← SRC1[127:64]
DEST[VLMAX-1:128] ← 0</pre>
<p><strong>VMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)</strong></p>
<pre>DEST[63:0] ← SRC2[63:0]
DEST[127:64] ← SRC1[127:64]
DEST[VLMAX-1:128] ← 0</pre>
<p><strong>VMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, m64)</strong></p>
<pre>DEST[63:0] ← SRC[63:0]
DEST[VLMAX-1:64] ← 0</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>MOVSD:</p>
<p>__m128d _mm_load_sd (double *p)</p>
<p>MOVSD:</p>
<p>void _mm_store_sd (double *p, __m128d a)</p>
<p>MOVSD:</p>
<p>__m128d _mm_store_sd (__m128d a, __m128d b)</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>See Exceptions Type 5; additionally</p>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>If VEX.vvvv ≠ 1111B.</td></tr></table></body></html>