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 <h1>FRSTOR—Restore x87 FPU State</h1>
 <table>
 <tr>
 <th>Opcode</th>
 <th>Instruction</th>
 <th>64-Bit Mode</th>
 <th>Compat/Leg Mode</th>
 <th>Description</th></tr>
 <tr>
 <td>DD /4</td>
 <td>FRSTOR <em>m94/108byte</em></td>
 <td>Valid</td>
 <td>Valid</td>
 <td>Load FPU state from <em>m94byte</em> or <em>m108byte</em>.</td></tr></table>
 <h2>Description</h2>
 <p>Loads the FPU state (operating environment and register stack) from the memory area specified with the source operand. This state data is typically written to the specified memory location by a previous FSAVE/FNSAVE instruc-tion.</p>
 <p>The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1</em>, show the layout in memory of the stored environment, depending on the operating mode of the processor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately following the operating environment image.</p>
 <p>The FRSTOR instruction should be executed in the same operating mode as the corresponding FSAVE/FNSAVE instruction.</p>
 <p>If one or more unmasked exception bits are set in the new FPU status word, a floating-point exception will be generated. To avoid raising exceptions when loading a new operating environment, clear all the exception flags in the FPU status word that is being loaded.</p>
 <p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
 <h2>Operation</h2>
 <pre>FPUControlWord ← SRC[FPUControlWord];
 FPUStatusWord ← SRC[FPUStatusWord];
 FPUTagWord ← SRC[FPUTagWord];
 FPUDataPointer ← SRC[FPUDataPointer];
 FPUInstructionPointer ← SRC[FPUInstructionPointer];
 FPULastInstructionOpcode ← SRC[FPULastInstructionOpcode];
 ST(0) ← SRC[ST(0)];
 ST(1) ← SRC[ST(1)];
 ST(2) ← SRC[ST(2)];
 ST(3) ← SRC[ST(3)];
 ST(4) ← SRC[ST(4)];
 ST(5) ← SRC[ST(5)];
 ST(6) ← SRC[ST(6)];
 ST(7) ← SRC[ST(7)];</pre>
 <h2>FPU Flags Affected</h2>
 <p>The C0, C1, C2, C3 flags are loaded.</p>
 <h2>Floating-Point Exceptions</h2>
 <p>None; however, this operation might unmask an existing exception that has been detected but not generated, because it was masked. Here, the exception is generated at the completion of the instruction.</p>
 <h2>Protected Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP(0)</td>
 <td>
 <p>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</p>
 <p>If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.</p></td></tr>
 <tr>
 <td>#SS(0)</td>
 <td>If a memory operand effective address is outside the SS segment limit.</td></tr>
 <tr>
 <td>#NM</td>
 <td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
 <tr>
 <td>#PF(fault-code)</td>
 <td>If a page fault occurs.</td></tr>
 <tr>
 <td>#AC(0)</td>
 <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
 <tr>
 <td>#UD</td>
 <td>If the LOCK prefix is used.</td></tr></table>
 <h2>Real-Address Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP</td>
 <td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
 <tr>
 <td>#SS</td>
 <td>If a memory operand effective address is outside the SS segment limit.</td></tr>
 <tr>
 <td>#NM</td>
 <td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
 <tr>
 <td>#UD</td>
 <td>If the LOCK prefix is used.</td></tr></table>
 <h2>Virtual-8086 Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#GP(0)</td>
 <td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
 <tr>
 <td>#SS(0)</td>
 <td>If a memory operand effective address is outside the SS segment limit.</td></tr>
 <tr>
 <td>#NM</td>
 <td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
 <tr>
 <td>#PF(fault-code)</td>
 <td>If a page fault occurs.</td></tr>
 <tr>
 <td>#AC(0)</td>
 <td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr>
 <tr>
 <td>#UD</td>
 <td>If the LOCK prefix is used.</td></tr></table>
 <h2>Compatibility Mode Exceptions</h2>
 <p>Same exceptions as in protected mode.</p>
 <h2>64-Bit Mode Exceptions</h2>
 <table class="exception-table">
 <tr>
 <td>#SS(0)</td>
 <td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
 <tr>
 <td>#GP(0)</td>
 <td>If the memory address is in a non-canonical form.</td></tr>
 <tr>
 <td>#NM</td>
 <td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
 <tr>
 <td>#PF(fault-code)</td>
 <td>If a page fault occurs.</td></tr>
 <tr>
 <td>#AC(0)</td>
 <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
 <tr>
 <td>#UD</td>
 <td>If the LOCK prefix is used.</td></tr></table></body></html>
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	<html>
	<head>
	<meta charset="UTF-8">
	<link href="style.css" type="text/css" rel="stylesheet">
	<title>FRSTOR—Restore x87 FPU State </title></head>
	<body>
	<h1>FRSTOR—Restore x87 FPU State</h1>
	<table>
	<tr>
	<th>Opcode</th>
	<th>Instruction</th>
	<th>64-Bit Mode</th>
	<th>Compat/Leg Mode</th>
	<th>Description</th></tr>
	<tr>
	<td>DD /4</td>
	<td>FRSTOR <em>m94/108byte</em></td>
	<td>Valid</td>
	<td>Valid</td>
	<td>Load FPU state from <em>m94byte</em> or <em>m108byte</em>.</td></tr></table>
	<h2>Description</h2>
	<p>Loads the FPU state (operating environment and register stack) from the memory area specified with the source operand. This state data is typically written to the specified memory location by a previous FSAVE/FNSAVE instruc-tion.</p>
	<p>The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1</em>, show the layout in memory of the stored environment, depending on the operating mode of the processor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately following the operating environment image.</p>
	<p>The FRSTOR instruction should be executed in the same operating mode as the corresponding FSAVE/FNSAVE instruction.</p>
	<p>If one or more unmasked exception bits are set in the new FPU status word, a floating-point exception will be generated. To avoid raising exceptions when loading a new operating environment, clear all the exception flags in the FPU status word that is being loaded.</p>
	<p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
	<h2>Operation</h2>
	<pre>FPUControlWord ← SRC[FPUControlWord];
	FPUStatusWord ← SRC[FPUStatusWord];
	FPUTagWord ← SRC[FPUTagWord];
	FPUDataPointer ← SRC[FPUDataPointer];
	FPUInstructionPointer ← SRC[FPUInstructionPointer];
	FPULastInstructionOpcode ← SRC[FPULastInstructionOpcode];
	ST(0) ← SRC[ST(0)];
	ST(1) ← SRC[ST(1)];
	ST(2) ← SRC[ST(2)];
	ST(3) ← SRC[ST(3)];
	ST(4) ← SRC[ST(4)];
	ST(5) ← SRC[ST(5)];
	ST(6) ← SRC[ST(6)];
	ST(7) ← SRC[ST(7)];</pre>
	<h2>FPU Flags Affected</h2>
	<p>The C0, C1, C2, C3 flags are loaded.</p>
	<h2>Floating-Point Exceptions</h2>
	<p>None; however, this operation might unmask an existing exception that has been detected but not generated, because it was masked. Here, the exception is generated at the completion of the instruction.</p>
	<h2>Protected Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP(0)</td>
	<td>
	<p>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</p>
	<p>If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.</p></td></tr>
	<tr>
	<td>#SS(0)</td>
	<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
	<tr>
	<td>#NM</td>
	<td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
	<tr>
	<td>#PF(fault-code)</td>
	<td>If a page fault occurs.</td></tr>
	<tr>
	<td>#AC(0)</td>
	<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
	<tr>
	<td>#UD</td>
	<td>If the LOCK prefix is used.</td></tr></table>
	<h2>Real-Address Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP</td>
	<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
	<tr>
	<td>#SS</td>
	<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
	<tr>
	<td>#NM</td>
	<td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
	<tr>
	<td>#UD</td>
	<td>If the LOCK prefix is used.</td></tr></table>
	<h2>Virtual-8086 Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#GP(0)</td>
	<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
	<tr>
	<td>#SS(0)</td>
	<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
	<tr>
	<td>#NM</td>
	<td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
	<tr>
	<td>#PF(fault-code)</td>
	<td>If a page fault occurs.</td></tr>
	<tr>
	<td>#AC(0)</td>
	<td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr>
	<tr>
	<td>#UD</td>
	<td>If the LOCK prefix is used.</td></tr></table>
	<h2>Compatibility Mode Exceptions</h2>
	<p>Same exceptions as in protected mode.</p>
	<h2>64-Bit Mode Exceptions</h2>
	<table class="exception-table">
	<tr>
	<td>#SS(0)</td>
	<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
	<tr>
	<td>#GP(0)</td>
	<td>If the memory address is in a non-canonical form.</td></tr>
	<tr>
	<td>#NM</td>
	<td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
	<tr>
	<td>#PF(fault-code)</td>
	<td>If a page fault occurs.</td></tr>
	<tr>
	<td>#AC(0)</td>
	<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
	<tr>
	<td>#UD</td>
	<td>If the LOCK prefix is used.</td></tr></table></body></html>