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| <title>CVTSI2SD—Convert Dword Integer to Scalar Double-Precision FP Value </title></head> |
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| <h1>CVTSI2SD—Convert Dword Integer to Scalar Double-Precision FP Value</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32-bit Mode</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>F2 0F 2A /<em>r</em></p> |
| <p>CVTSI2SD <em>xmm</em>, <em>r/m32</em></p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE2</td> |
| <td>Convert one signed doubleword integer from <em>r/m32</em> to one double-precision floating-point value in <em>xmm</em>.</td></tr> |
| <tr> |
| <td> |
| <p>F2 REX.W 0F 2A /<em>r</em></p> |
| <p>CVTSI2SD <em>xmm</em>, <em>r/m64</em></p></td> |
| <td>RM</td> |
| <td>V/N.E.</td> |
| <td>SSE2</td> |
| <td>Convert one signed quadword integer from <em>r/m64</em> to one double-precision floating-point value in <em>xmm</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.NDS.LIG.F2.0F.W0 2A /r</p> |
| <p>VCVTSI2SD xmm1, xmm2, r/m32</p></td> |
| <td>RVM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Convert one signed doubleword integer from r/m32 to one double-precision floating-point value in xmm1.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.NDS.LIG.F2.0F.W1 2A /r</p> |
| <p>VCVTSI2SD xmm1, xmm2, r/m64</p></td> |
| <td>RVM</td> |
| <td>V/N.E.<sup>1</sup></td> |
| <td>AVX</td> |
| <td>Convert one signed quadword integer from r/m64 to one double-precision floating-point value in xmm1.</td></tr></table> |
| <p><strong>NOTES:</strong></p> |
| <p>1. Encoding the VEX prefix with VEX.W=1 in non-64-bit mode is ignored.</p> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RVM</td> |
| <td>ModRM:reg (w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the second source operand to a double-precision floating-point value in the destination operand. The result is stored in the low quad-word of the destination operand, and the high quadword left unchanged. When conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.</p> |
| <p>Legacy SSE instructions: Use of the REX.W prefix promotes the instruction to 64-bit operands. See the summary chart at the beginning of this section for encoding data and limits.</p> |
| <p>The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and destination operands are XMM registers.</p> |
| <p>128-bit Legacy SSE version: The destination and first source operand are the same. Bits (VLMAX-1:64) of the corresponding YMM destination register remain unchanged.</p> |
| <p>VEX.128 encoded version: Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p> |
| <h2>Operation</h2> |
| <p><strong>CVTSI2SD</strong></p> |
| <pre>IF 64-Bit Mode And OperandSize = 64 |
| THEN |
| DEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:0]); |
| ELSE |
| DEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]); |
| FI; |
| DEST[VLMAX-1:64] (Unmodified)</pre> |
| <p><strong>VCVTSI2SD</strong></p> |
| <pre>IF 64-Bit Mode And OperandSize = 64 |
| THEN |
| DEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]); |
| ELSE |
| DEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]); |
| FI; |
| DEST[127:64] ← SRC1[127:64] |
| DEST[VLMAX-1:128] ← 0</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>CVTSI2SD:</p> |
| <p>__m128d _mm_cvtsi32_sd(__m128d a, int b)</p> |
| <p>CVTSI2SD:</p> |
| <p>__m128d _mm_cvtsi64_sd(__m128d a, __int64 b)</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>Precision.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 3.</p></body></html> |