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| <title>CVTSD2SI—Convert Scalar Double-Precision FP Value to Integer </title></head> |
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| <h1>CVTSD2SI—Convert Scalar Double-Precision FP Value to Integer</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32-bit Mode</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>F2 0F 2D /<em>r</em></p> |
| <p>CVTSD2SI <em>r32</em>, <em>xmm/m64</em></p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE2</td> |
| <td>Convert one double-precision floating-point value from <em>xmm/m64</em> to one signed doubleword integer <em>r32</em>.</td></tr> |
| <tr> |
| <td> |
| <p> F2 REX.W 0F 2D /<em>r</em></p> |
| <p>CVTSD2SI <em>r64</em>, <em>xmm/m64</em></p></td> |
| <td>RM</td> |
| <td>V/N.E.</td> |
| <td>SSE2</td> |
| <td>Convert one double-precision floating-point value from <em>xmm/m64</em> to one signed quadword integer sign-extended into <em>r64</em>.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.LIG.F2.0F.W0 2D /r</p> |
| <p>VCVTSD2SI r32, xmm1/m64</p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Convert one double precision floating-point value from xmm1/m64 to one signed doubleword integer r32.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.LIG.F2.0F.W1 2D /r</p> |
| <p>VCVTSD2SI r64, xmm1/m64</p></td> |
| <td>RM</td> |
| <td>V/N.E.<sup>1</sup></td> |
| <td>AVX</td> |
| <td>Convert one double precision floating-point value from xmm1/m64 to one signed quadword integer sign-extended into r64.</td></tr></table> |
| <p><strong>NOTES:</strong></p> |
| <p>1. Encoding the VEX prefix with VEX.W=1 in non-64-bit mode is ignored.</p> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Converts a double-precision floating-point value in the source operand (second operand) to a signed doubleword integer in the destination operand (first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the double-precision floating-point value is contained in the low quadword of the register.</p> |
| <p>When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.</p> |
| <p>In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the instruction to 64-bit operation. See the summary chart at the begin-ning of this section for encoding data and limits.</p> |
| <p>Legacy SSE instructions: Use of the REX.W prefix promotes the instruction to 64-bit operation. See the summary chart at the beginning of this section for encoding data and limits.</p> |
| <p>Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p> |
| <h2>Operation</h2> |
| <pre>IF 64-Bit Mode and OperandSize = 64 |
| THEN |
| DEST[63:0] ← Convert_Double_Precision_Floating_Point_To_Integer64(SRC[63:0]); |
| ELSE |
| DEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]); |
| FI;</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>int _mm_cvtsd_si32(__m128d a)</p> |
| <p>__int64 _mm_cvtsd_si64(__m128d a)</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>Invalid, Precision.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 3; additionally</p> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td>If VEX.vvvv ≠ 1111B.</td></tr></table></body></html> |