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| <title>COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS </title></head> |
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| <h1>COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32-bit Mode</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>0F 2F /<em>r</em></p> |
| <p>COMISS <em>xmm1</em>,<em> xmm2/m32</em></p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>SSE</td> |
| <td>Compare low single-precision floating-point values in <em>xmm1</em> and <em>xmm2/mem32</em> and set the EFLAGS flags accordingly.</td></tr> |
| <tr> |
| <td> |
| <p>VEX.LIG.0F.WIG 2F /r</p> |
| <p>VCOMISS xmm1, xmm2/m32</p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>AVX</td> |
| <td>Compare low single precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Compares the single-precision floating-point values in the low doublewords of operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unor-dered, greater than, less than, or equal). The OF, SF, and AF flags in the EFLAGS register are set to 0. The unor-dered result is returned if either source operand is a NaN (QNaN or SNaN). The sign of zero is ignored for comparisons, so that –0.0 is equal to +0.0.</p> |
| <p>Operand 1 is an XMM register; Operand 2 can be an XMM register or a 32 bit memory location.</p> |
| <p>The COMISS instruction differs from the UCOMISS instruction in that it signals a SIMD floating-point invalid opera-tion exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISS instruction signals an invalid numeric exception only if a source operand is an SNaN.</p> |
| <p>The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.</p> |
| <p>In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).</p> |
| <p>Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p> |
| <h2>Operation</h2> |
| <pre>RESULT ← OrderedCompare(SRC1[31:0] ≠ SRC2[31:0]) { |
| (* Set EFLAGS *) CASE (RESULT) OF |
| UNORDERED: |
| ZF,PF,CF ← 111; |
| GREATER_THAN: |
| ZF,PF,CF ← 000; |
| LESS_THAN: |
| ZF,PF,CF ← 001; |
| EQUAL: |
| ZF,PF,CF ← 100; |
| ESAC; |
| OF,AF,SF ← 0; }</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalents</h2> |
| <p>int _mm_comieq_ss (__m128 a, __m128 b)</p> |
| <p>int _mm_comilt_ss (__m128 a, __m128 b)</p> |
| <p>int _mm_comile_ss (__m128 a, __m128 b)</p> |
| <p>int _mm_comigt_ss (__m128 a, __m128 b)</p> |
| <p>int _mm_comige_ss (__m128 a, __m128 b)</p> |
| <p>int _mm_comineq_ss (__m128 a, __m128 b)</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>Invalid (if SNaN or QNaN operands), Denormal.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 3; additionally</p> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td>If VEX.vvvv ≠ 1111B.</td></tr></table></body></html> |