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| <title>BSR—Bit Scan Reverse </title></head> |
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| <h1>BSR—Bit Scan Reverse</h1> |
| <table> |
| <tr> |
| <th>Opcode</th> |
| <th>Instruction</th> |
| <th>Op/En</th> |
| <th>64-bit Mode</th> |
| <th>Compat/Leg Mode</th> |
| <th>Description</th></tr> |
| <tr> |
| <td>0F BD /r</td> |
| <td>BSR <em>r16, r/m16</em></td> |
| <td>RM</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Bit scan reverse on <em>r/m16.</em></td></tr> |
| <tr> |
| <td>0F BD /r</td> |
| <td>BSR <em>r32, r/m32</em></td> |
| <td>RM</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Bit scan reverse on <em>r/m32.</em></td></tr> |
| <tr> |
| <td>REX.W + 0F BD /r</td> |
| <td>BSR <em>r64, r/m64</em></td> |
| <td>RM</td> |
| <td>Valid</td> |
| <td>N.E.</td> |
| <td>Bit scan reverse on <em>r/m64.</em></td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Searches the source operand (second operand) for the most significant set bit (1 bit). If a most significant 1 bit is found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a memory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source operand. If the content source operand is 0, the content of the destination operand is undefined.</p> |
| <p>In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p> |
| <h2>Operation</h2> |
| <pre>IF SRC = 0 |
| THEN |
| ZF ← 1; |
| DEST is undefined; |
| ELSE |
| ZF ← 0; |
| temp ← OperandSize – 1; |
| WHILE Bit(SRC, temp) = 0 |
| DO |
| temp ← temp - 1; |
| OD; |
| DEST ← temp; |
| FI;</pre> |
| <h2>Flags Affected</h2> |
| <p>The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags are undefined.</p> |
| <h2>Protected Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#GP(0)</td> |
| <td> |
| <p>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</p> |
| <p>If the DS, ES, FS, or GS register contains a NULL segment selector.</p></td></tr> |
| <tr> |
| <td>#SS(0)</td> |
| <td>If a memory operand effective address is outside the SS segment limit.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>If a page fault occurs.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td>If the LOCK prefix is used.</td></tr></table> |
| <h2>Real-Address Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#GP</td> |
| <td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr> |
| <tr> |
| <td>#SS</td> |
| <td>If a memory operand effective address is outside the SS segment limit.</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td>If the LOCK prefix is used.</td></tr></table> |
| <h2>Virtual-8086 Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr> |
| <tr> |
| <td>#SS(0)</td> |
| <td>If a memory operand effective address is outside the SS segment limit.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>If a page fault occurs.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td>If the LOCK prefix is used.</td></tr></table> |
| <h2>Compatibility Mode Exceptions</h2> |
| <p>Same exceptions as in protected mode.</p> |
| <h2>64-Bit Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#SS(0)</td> |
| <td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If the memory address is in a non-canonical form.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>If a page fault occurs.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td>If the LOCK prefix is used.</td></tr></table></body></html> |