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| <title>ADCX — Unsigned Integer Addition of Two Operands with Carry Flag </title></head> |
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| <h1>ADCX — Unsigned Integer Addition of Two Operands with Carry Flag</h1> |
| <table> |
| <tr> |
| <th>Opcode/Instruction</th> |
| <th>Op/En</th> |
| <th>64/32bit Mode Support</th> |
| <th>CPUID Feature Flag</th> |
| <th>Description</th></tr> |
| <tr> |
| <td> |
| <p>66 0F 38 F6 /r</p> |
| <p>ADCX r32, r/m32</p></td> |
| <td>RM</td> |
| <td>V/V</td> |
| <td>ADX</td> |
| <td>Unsigned addition of r32 with CF, r/m32 to r32, writes CF.</td></tr> |
| <tr> |
| <td> |
| <p>REX.w + 66 0F 38 F6 /r</p> |
| <p>ADCX r64, r/m64</p></td> |
| <td>RM</td> |
| <td>V/NE</td> |
| <td>ADX</td> |
| <td>Unsigned addition of r64 with CF, r/m64 to r64, writes CF.</td></tr></table> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Performs an unsigned addition of the destination operand (first operand), the source operand (second operand) and the carry-flag (CF) and stores the result in the destination operand. The destination operand is a general-purpose register, whereas the source operand can be a general-purpose register or memory location. The state of CF can represent a carry from a previous addition. The instruction sets the CF flag with the carry generated by the unsigned addition of the operands.</p> |
| <p>The ADCX instruction is executed in the context of multi-precision addition, where we add a series of operands with a carry-chain. At the beginning of a chain of additions, we need to make sure the CF is in a desired initial state. Often, this initial state needs to be 0, which can be achieved with an instruction to zero the CF (e.g. XOR).</p> |
| <p>This instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode.</p> |
| <p>In 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to addi-tional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64 bits.</p> |
| <p>ADCX executes normally either inside or outside a transaction region.</p> |
| <p>Note: ADCX defines the OF flag differently than the ADD/ADC instructions as defined in <em>Intel<sup>®</sup> 64 and IA-32 Archi-tectures Software Developer’s Manual, Volume 2A</em>.</p> |
| <h2>Operation</h2> |
| <pre>IF OperandSize is 64-bit |
| THEN CF:DEST[63:0] ← DEST[63:0] + SRC[63:0] + CF; |
| ELSE CF:DEST[31:0] ← DEST[31:0] + SRC[31:0] + CF; |
| FI;</pre> |
| <h2>Flags Affected</h2> |
| <p>CF is updated based on result. OF, SF, ZF, AF and PF flags are unmodified.</p> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2> |
| <p>unsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);</p> |
| <p>unsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);</p> |
| <h2>SIMD Floating-Point Exceptions</h2> |
| <p>None</p> |
| <h2>Protected Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If the LOCK prefix is used.</p> |
| <p>If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.</p></td></tr> |
| <tr> |
| <td>#SS(0)</td> |
| <td>For an illegal address in the SS segment.</td></tr> |
| <tr> |
| <td>#GP(0)</td> |
| <td> |
| <p>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</p> |
| <p>If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</p></td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>For a page fault.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table> |
| <h2>Real-Address Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If the LOCK prefix is used.</p> |
| <p>If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.</p></td></tr> |
| <tr> |
| <td>#SS(0)</td> |
| <td>For an illegal address in the SS segment.</td></tr> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr></table> |
| <h2>Virtual-8086 Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If the LOCK prefix is used.</p> |
| <p>If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.</p></td></tr> |
| <tr> |
| <td>#SS(0)</td> |
| <td>For an illegal address in the SS segment.</td></tr> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>For a page fault.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table> |
| <h2>Compatibility Mode Exceptions</h2> |
| <p>Same exceptions as in protected mode.</p> |
| <h2>64-Bit Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If the LOCK prefix is used.</p> |
| <p>If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.</p></td></tr> |
| <tr> |
| <td>#SS(0)</td> |
| <td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If the memory address is in a non-canonical form.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>For a page fault.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table></body></html> |