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| <title>SGDT—Store Global Descriptor Table Register </title></head> |
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| <h1>SGDT—Store Global Descriptor Table Register</h1> |
| <table> |
| <tr> |
| <th>Opcode*</th> |
| <th>Instruction</th> |
| <th>Op/En</th> |
| <th>64-Bit Mode</th> |
| <th>Compat/Leg Mode</th> |
| <th>Description</th></tr> |
| <tr> |
| <td>0F 01 /0</td> |
| <td>SGDT <em>m</em></td> |
| <td>M</td> |
| <td>Valid</td> |
| <td>Valid</td> |
| <td>Store GDTR to <em>m.</em></td></tr></table> |
| <p><strong>NOTES:</strong></p> |
| <p>*</p> |
| <p>See IA-32 Architecture Compatibility section below.</p> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>M</td> |
| <td>ModRM:r/m (w)</td> |
| <td>NA</td> |
| <td>NA</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Stores the content of the global descriptor table register (GDTR) in the destination operand. The destination operand specifies a memory location.</p> |
| <p>In legacy or compatibility mode, the destination operand is a 6-byte memory location. If the operand-size attribute is 16 bits, the limit is stored in the low 2 bytes and the 24-bit base address is stored in bytes 3-5, and byte 6 is zero-filled. If the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the low 2 bytes of the memory location and the 32-bit base address is stored in the high 4 bytes.</p> |
| <p>In IA-32e mode, the operand size is fixed at 8+2 bytes. The instruction stores an 8-byte base and a 2-byte limit.</p> |
| <p>SGDT is useful only by operating-system software. However, it can be used in application programs without causing an exception to be generated. See “LGDT/LIDT—Load Global/Interrupt Descriptor Table Register” in Chapter 3, <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em>, for information on loading the GDTR and IDTR.</p> |
| <h2>IA-32 Architecture Compatibility</h2> |
| <p>The 16-bit form of the SGDT is compatible with the Intel 286 processor if the upper 8 bits are not referenced. The Intel 286 processor fills these bits with 1s; the Pentium 4, Intel Xeon, P6 processor family, Pentium, Intel486, and Intel386™ processors fill these bits with 0s.</p> |
| <h2>Operation</h2> |
| <pre>IF instruction is SGDT |
| IF OperandSize = 16 |
| THEN |
| DEST[0:15] ← GDTR(Limit); |
| DEST[16:39] ← GDTR(Base); (* 24 bits of base address stored *) |
| DEST[40:47] ← 0; |
| ELSE IF (32-bit Operand Size) |
| DEST[0:15] ← GDTR(Limit); |
| DEST[16:47] ← GDTR(Base); (* Full 32-bit base address stored *) |
| FI; |
| ELSE (* 64-bit Operand Size *) |
| DEST[0:15] ← GDTR(Limit); |
| DEST[16:79] ← GDTR(Base); (* Full 64-bit base address stored *) |
| FI; |
| FI;</pre> |
| <h2>Flags Affected</h2> |
| <p>None.</p> |
| <h2>Protected Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If the destination operand is a register.</p> |
| <p>If the LOCK prefix is used.</p></td></tr> |
| <tr> |
| <td>#GP(0)</td> |
| <td> |
| <p>If the destination is located in a non-writable segment.</p> |
| <p>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</p> |
| <p>If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.</p></td></tr> |
| <tr> |
| <td>#SS(0)</td> |
| <td>If a memory operand effective address is outside the SS segment limit.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>If a page fault occurs.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table> |
| <h2>Real-Address Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If the destination operand is a register.</p> |
| <p>If the LOCK prefix is used.</p></td></tr> |
| <tr> |
| <td>#GP</td> |
| <td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr> |
| <tr> |
| <td>#SS</td> |
| <td>If a memory operand effective address is outside the SS segment limit.</td></tr></table> |
| <h2>Virtual-8086 Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If the destination operand is a register.</p> |
| <p>If the LOCK prefix is used.</p></td></tr> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr> |
| <tr> |
| <td>#SS(0)</td> |
| <td>If a memory operand effective address is outside the SS segment limit.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>If a page fault occurs.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr></table> |
| <h2>Compatibility Mode Exceptions</h2> |
| <p>Same exceptions as in protected mode.</p> |
| <h2>64-Bit Mode Exceptions</h2> |
| <table class="exception-table"> |
| <tr> |
| <td>#SS(0)</td> |
| <td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr> |
| <tr> |
| <td>#UD</td> |
| <td> |
| <p>If the destination operand is a register.</p> |
| <p>If the LOCK prefix is used.</p></td></tr> |
| <tr> |
| <td>#GP(0)</td> |
| <td>If the memory address is in a non-canonical form.</td></tr> |
| <tr> |
| <td>#PF(fault-code)</td> |
| <td>If a page fault occurs.</td></tr> |
| <tr> |
| <td>#AC(0)</td> |
| <td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table></body></html> |