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| <title>PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical </title></head> |
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| <h1>PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical</h1> |
| <p><strong>Description</strong></p> |
| <p><strong>CPUID</strong></p> |
| <p><strong>Opcode/</strong></p> |
| <p><strong>Op/</strong></p> |
| <p><strong>64/32 bit</strong></p> |
| <p><strong>Feature</strong></p> |
| <p><strong>Instruction</strong></p> |
| <p><strong>En</strong></p> |
| <p><strong>Mode</strong></p> |
| <p><strong>Flag</strong></p> |
| <p><strong>Support</strong></p> |
| <p>0F D1 /<em>r</em><sup>1</sup></p> |
| <p>RM</p> |
| <p>V/V</p> |
| <p>MMX</p> |
| <p>Shift words in <em>mm</em> right by amount specified in <em>mm/m64</em> while shifting in 0s.</p> |
| <p>PSRLW <em>mm, mm/m64</em></p> |
| <p>66 0F D1 /<em>r</em></p> |
| <p>RM</p> |
| <p>V/V</p> |
| <p>SSE2</p> |
| <p>Shift words in <em>xmm1</em> right by amount specified in <em>xmm2/m128</em> while shifting in 0s.</p> |
| <p>PSRLW <em>xmm1</em>, <em>xmm2/m128</em></p> |
| <p>MI</p> |
| <p>V/V</p> |
| <p>MMX</p> |
| <p>Shift words in <em>mm</em> right by <em>imm8</em> while shifting</p> |
| <p>0F 71 /2 ib<sup>1</sup></p> |
| <p>in 0s.</p> |
| <p>PSRLW <em>mm, imm8</em></p> |
| <p>66 0F 71 /2 ib</p> |
| <p>MI</p> |
| <p>V/V</p> |
| <p>SSE2</p> |
| <p>Shift words in <em>xmm1</em> right by <em>imm8</em> while shifting in 0s.</p> |
| <p>PSRLW <em>xmm1</em>, <em>imm8</em></p> |
| <p>RM</p> |
| <p>V/V</p> |
| <p>MMX</p> |
| <p>Shift doublewords in <em>mm</em> right by amount</p> |
| <p>0F D2 /<em>r</em><sup>1</sup></p> |
| <p>specified in <em>mm/m64</em> while shifting in 0s.</p> |
| <p>PSRLD <em>mm, mm/m64</em></p> |
| <p>66 0F D2 /<em>r</em></p> |
| <p>RM</p> |
| <p>V/V</p> |
| <p>SSE2</p> |
| <p>Shift doublewords in <em>xmm1</em> right by amount specified in <em>xmm2 /m128</em> while shifting in 0s.</p> |
| <p>PSRLD <em>xmm1</em>, <em>xmm2/m128</em></p> |
| <p>0F 72 /2 ib<sup>1</sup></p> |
| <p>MI</p> |
| <p>V/V</p> |
| <p>MMX</p> |
| <p>Shift doublewords in <em>mm</em> right by <em>imm8</em> while shifting in 0s.</p> |
| <p>PSRLD <em>mm, imm8</em></p> |
| <p>66 0F 72 /2 ib</p> |
| <p>MI</p> |
| <p>V/V</p> |
| <p>SSE2</p> |
| <p>Shift doublewords in <em>xmm1</em> right by <em>imm8 </em>while shifting in 0s.</p> |
| <p>PSRLD <em>xmm1</em>, imm8</p> |
| <p>RM</p> |
| <p>V/V</p> |
| <p>MMX</p> |
| <p>Shift <em>mm</em> right by amount specified in</p> |
| <p>0F D3 /<em>r</em><sup>1</sup></p> |
| <p><em>mm/m64</em> while shifting in 0s.</p> |
| <p>PSRLQ <em>mm, mm/m64</em></p> |
| <p>66 0F D3 /<em>r</em></p> |
| <p>RM</p> |
| <p>V/V</p> |
| <p>SSE2</p> |
| <p>Shift quadwords in <em>xmm1</em> right by amount specified in <em>xmm2/m128</em> while shifting in 0s.</p> |
| <p>PSRLQ <em>xmm1</em>, <em>xmm2/m128</em></p> |
| <p>MI</p> |
| <p>V/V</p> |
| <p>MMX</p> |
| <p>Shift <em>mm</em> right by <em>imm8</em> while shifting in 0s.</p> |
| <p>0F 73 /2 ib<sup>1</sup></p> |
| <p>PSRLQ <em>mm, imm8</em></p> |
| <p>66 0F 73 /2 ib</p> |
| <p>MI</p> |
| <p>V/V</p> |
| <p>SSE2</p> |
| <p>Shift quadwords in <em>xmm1</em> right by <em>imm8</em> while shifting in 0s.</p> |
| <p>PSRLQ <em>xmm1</em>, <em>imm8</em></p> |
| <p>VEX.NDS.128.66.0F.WIG D1 /r</p> |
| <p>RVM</p> |
| <p>V/V</p> |
| <p>AVX</p> |
| <p>Shift words in <em>xmm2</em> right by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p> |
| <p>VPSRLW <em>xmm1, xmm2, xmm3/m128</em></p> |
| <p>VEX.NDD.128.66.0F.WIG 71 /2 ib</p> |
| <p>VMI</p> |
| <p>V/V</p> |
| <p>AVX</p> |
| <p>Shift words in <em>xmm2</em> right by <em>imm8</em> while shifting in 0s.</p> |
| <p>VPSRLW <em>xmm1, xmm2, imm8</em></p> |
| <p>VEX.NDS.128.66.0F.WIG D2 /r</p> |
| <p>RVM</p> |
| <p>V/V</p> |
| <p>AVX</p> |
| <p>Shift doublewords in <em>xmm2</em> right by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p> |
| <p>VPSRLD <em>xmm1, xmm2, xmm3/m128</em></p> |
| <p>VEX.NDD.128.66.0F.WIG 72 /2 ib</p> |
| <p>VMI</p> |
| <p>V/V</p> |
| <p>AVX</p> |
| <p>Shift doublewords in <em>xmm2</em> right by <em>imm8 </em>while shifting in 0s.</p> |
| <p>VPSRLD <em>xmm1, xmm2, imm8</em></p> |
| <p>VEX.NDS.128.66.0F.WIG D3 /r</p> |
| <p>RVM</p> |
| <p>V/V</p> |
| <p>AVX</p> |
| <p>Shift quadwords in <em>xmm2</em> right by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p> |
| <p>VPSRLQ <em>xmm1, xmm2, xmm3/m128</em></p> |
| <p>VEX.NDD.128.66.0F.WIG 73 /2 ib</p> |
| <p>VMI</p> |
| <p>V/V</p> |
| <p>AVX</p> |
| <p>Shift quadwords in <em>xmm2</em> right by <em>imm8</em> while shifting in 0s.</p> |
| <p>VPSRLQ <em>xmm1, xmm2, imm8</em></p> |
| <p>VEX.NDS.256.66.0F.WIG D1 /r</p> |
| <p>RVM</p> |
| <p>V/V</p> |
| <p>AVX2</p> |
| <p>Shift words in <em>ymm2</em> right by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p> |
| <p>VPSRLW <em>ymm1, ymm2, xmm3/m128</em></p> |
| <p>VEX.NDD.256.66.0F.WIG 71 /2 ib</p> |
| <p>VMI</p> |
| <p>V/V</p> |
| <p>AVX2</p> |
| <p>Shift words in <em>ymm2</em> right by <em>imm8</em> while shifting in 0s.</p> |
| <p>VPSRLW <em>ymm1, ymm2, imm8</em></p> |
| <p>VEX.NDS.256.66.0F.WIG D2 /r</p> |
| <p>RVM</p> |
| <p>V/V</p> |
| <p>AVX2</p> |
| <p>Shift doublewords in <em>ymm2</em> right by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p> |
| <p>VPSRLD <em>ymm1, ymm2, xmm3/m128</em></p> |
| <p>VEX.NDD.256.66.0F.WIG 72 /2 ib</p> |
| <p>VMI</p> |
| <p>V/V</p> |
| <p>AVX2</p> |
| <p>Shift doublewords in <em>ymm2</em> right by <em>imm8 </em>while shifting in 0s.</p> |
| <p>VPSRLD <em>ymm1, ymm2, imm8</em></p> |
| <p>VEX.NDS.256.66.0F.WIG D3 /r</p> |
| <p>RVM</p> |
| <p>V/V</p> |
| <p>AVX2</p> |
| <p>Shift quadwords in <em>ymm2</em> right by amount specified in <em>xmm3/m128</em> while shifting in 0s.</p> |
| <p>VPSRLQ <em>ymm1, ymm2, xmm3/m128</em></p> |
| <p>VEX.NDD.256.66.0F.WIG 73 /2 ib</p> |
| <p>VMI</p> |
| <p>V/V</p> |
| <p>AVX2</p> |
| <p>Shift quadwords in <em>ymm2</em> right by <em>imm8</em> while shifting in 0s.</p> |
| <p>VPSRLQ <em>ymm1, ymm2, imm8</em></p> |
| <p>NOTES:</p> |
| <p>1. See note in Section 2.4, “Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p> |
| <h3>Instruction Operand Encoding</h3> |
| <table> |
| <tr> |
| <td>Op/En</td> |
| <td>Operand 1</td> |
| <td>Operand 2</td> |
| <td>Operand 3</td> |
| <td>Operand 4</td></tr> |
| <tr> |
| <td>RM</td> |
| <td>ModRM:reg (r, w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>MI</td> |
| <td>ModRM:r/m (r, w)</td> |
| <td>imm8</td> |
| <td>NA</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>RVM</td> |
| <td>ModRM:reg (w)</td> |
| <td>VEX.vvvv (r)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>NA</td></tr> |
| <tr> |
| <td>VMI</td> |
| <td>VEX.vvvv (w)</td> |
| <td>ModRM:r/m (r)</td> |
| <td>imm8</td> |
| <td>NA</td></tr></table> |
| <h2>Description</h2> |
| <p>Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data elements are shifted right, the empty high-order bits are cleared (set to 0). If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand is set to all 0s. Figure 4-15 gives an example of shifting words in a 64-bit operand.</p> |
| <p>Note that only the first 64-bits of a 128-bit count operand are checked to compute the count.</p> |
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| <text y="650719.907684" x="220.9198" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">X3</text> |
| <text y="650719.907684" x="284.635312" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">X2</text> |
| <text y="650719.907484" x="407.94" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.717246">X0</text> |
| <text y="650773.667384" x="262.6801" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="53.59916">X2 >> COUNT</text> |
| <text y="650773.667384" x="325.9199" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="53.5834">X1 >> COUNT</text> |
| <text y="650773.667184" x="386.5201" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="11.997132">X0 >> COUNT</text> |
| <text y="650773.667384" x="198.8998" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="53.65532">X3 >> COUNT</text> |
| <text y="650719.907684" x="345.653584" style="font-size:7.980000pt" lengthAdjust="spacingAndGlyphs" textLength="9.777096">X1</text></svg> |
| <h3>Figure 4-15. PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand</h3> |
| <p>The (V)PSRLW instruction shifts each of the words in the destination operand to the right by the number of bits specified in the count operand; the (V)PSRLD instruction shifts each of the doublewords in the destination operand; and the PSRLQ instruction shifts the quadword (or quadwords) in the destination operand.</p> |
| <p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p> |
| <p>Legacy SSE instructions: The destination operand is an MMX technology register; the count operand can be either an MMX technology register or an 64-bit memory location.</p> |
| <p>128-bit Legacy SSE version: The destination operand is an XMM register; the count operand can be either an XMM register or a 128-bit memory location, or an 8-bit immediate. If the count operand is a memory address, 128 bits</p> |
| <p>are loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p> |
| <p>VEX.128 encoded version: The destination operand is an XMM register; the count operand can be either an XMM register or a 128-bit memory location, or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p> |
| <p>VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be either an YMM register or a 128-bit memory location or an 8-bit immediate.</p> |
| <p>Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /2), VEX.vvvv encodes the destination register, and VEX.B + ModRM.r/m encodes the source register. VEX.L must be 0, otherwise instructions will #UD.</p> |
| <h2>Operation</h2> |
| <p><strong>PSRLW (with 64-bit operand)</strong></p> |
| <pre> IF (COUNT > 15) |
| THEN |
| DEST[64:0] ← 0000000000000000H |
| ELSE |
| DEST[15:0] ← ZeroExtend(DEST[15:0] >> COUNT); |
| (* Repeat shift operation for 2nd and 3rd words *) |
| DEST[63:48] ← ZeroExtend(DEST[63:48] >> COUNT); |
| FI;</pre> |
| <p><strong>PSRLD (with 64-bit operand)</strong></p> |
| <pre> IF (COUNT > 31) |
| THEN |
| DEST[64:0] ← 0000000000000000H |
| ELSE |
| DEST[31:0] ← ZeroExtend(DEST[31:0] >> COUNT); |
| DEST[63:32] ← ZeroExtend(DEST[63:32] >> COUNT); |
| FI;</pre> |
| <p><strong>PSRLQ (with 64-bit operand)</strong></p> |
| <pre> IF (COUNT > 63) |
| THEN |
| DEST[64:0] ← 0000000000000000H |
| ELSE |
| DEST ← ZeroExtend(DEST >> COUNT); |
| FI;</pre> |
| <p><strong>PSRLW (with 128-bit operand)</strong></p> |
| <pre> COUNT ← COUNT_SOURCE[63:0]; |
| IF (COUNT > 15) |
| THEN |
| DEST[128:0] ← 00000000000000000000000000000000H |
| ELSE |
| DEST[15:0] ← ZeroExtend(DEST[15:0] >> COUNT); |
| (* Repeat shift operation for 2nd through 7th words *) |
| DEST[127:112] ← ZeroExtend(DEST[127:112] >> COUNT); |
| FI;</pre> |
| <p><strong>PSRLD (with 128-bit operand)</strong></p> |
| <pre> COUNT ← COUNT_SOURCE[63:0]; |
| IF (COUNT > 31) |
| THEN |
| DEST[128:0] ← 00000000000000000000000000000000H |
| ELSE |
| DEST[31:0] ← ZeroExtend(DEST[31:0] >> COUNT); |
| (* Repeat shift operation for 2nd and 3rd doublewords *) |
| DEST[127:96] ← ZeroExtend(DEST[127:96] >> COUNT); |
| FI;</pre> |
| <p><strong>PSRLQ (with 128-bit operand)</strong></p> |
| <pre> COUNT ← COUNT_SOURCE[63:0]; |
| IF (COUNT > 15) |
| THEN |
| DEST[128:0] ← 00000000000000000000000000000000H |
| ELSE |
| DEST[63:0] ← ZeroExtend(DEST[63:0] >> COUNT); |
| DEST[127:64] ← ZeroExtend(DEST[127:64] >> COUNT); |
| FI;</pre> |
| <p><strong>PSRLW (xmm, xmm, xmm/m128)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_WORDS(DEST, SRC) |
| DEST[VLMAX-1:128] (Unmodified)</pre> |
| <p><strong>PSRLW (xmm, imm8)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_WORDS(DEST, imm8) |
| DEST[VLMAX-1:128] (Unmodified)</pre> |
| <p><strong>VPSRLW (xmm, xmm, xmm/m128)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_WORDS(SRC1, SRC2) |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VPSRLW (xmm, imm8)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_WORDS(SRC1, imm8) |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>PSRLD (xmm, xmm, xmm/m128)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_DWORDS(DEST, SRC) |
| DEST[VLMAX-1:128] (Unmodified)</pre> |
| <p><strong>PSRLD (xmm, imm8)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_DWORDS(DEST, imm8) |
| DEST[VLMAX-1:128] (Unmodified)</pre> |
| <p><strong>VPSRLD (xmm, xmm, xmm/m128)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, SRC2) |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VPSRLD (xmm, imm8)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, imm8) |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>PSRLQ (xmm, xmm, xmm/m128)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_QWORDS(DEST, SRC) |
| DEST[VLMAX-1:128] (Unmodified)</pre> |
| <p><strong>PSRLQ (xmm, imm8)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_QWORDS(DEST, imm8) |
| DEST[VLMAX-1:128] (Unmodified)</pre> |
| <p><strong>VPSRLQ (xmm, xmm, xmm/m128)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, SRC2) |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VPSRLQ (xmm, imm8)</strong></p> |
| <pre>DEST[127:0] ← LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, imm8) |
| DEST[VLMAX-1:128] ← 0</pre> |
| <p><strong>VPSRLW (ymm, ymm, xmm/m128)</strong></p> |
| <pre>DEST[255:0] ← LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)</pre> |
| <p><strong>VPSRLW (ymm, imm8)</strong></p> |
| <pre>DEST[255:0] ← LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)</pre> |
| <p><strong>VPSRLD (ymm, ymm, xmm/m128)</strong></p> |
| <pre>DEST[255:0] ← LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)</pre> |
| <p><strong>VPSRLD (ymm, imm8)</strong></p> |
| <pre>DEST[255:0] ← LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)</pre> |
| <p><strong>VPSRLQ (ymm, ymm, xmm/m128)</strong></p> |
| <pre>DEST[255:0] ← LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, SRC2)</pre> |
| <p><strong>VPSRLQ (ymm, imm8)</strong></p> |
| <pre>DEST[255:0] ← LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, imm8)</pre> |
| <h2>Intel C/C++ Compiler Intrinsic Equivalents</h2> |
| <p>PSRLW:</p> |
| <p>__m64 _mm_srli_pi16(__m64 m, int count)</p> |
| <p>PSRLW:</p> |
| <p>__m64 _mm_srl_pi16 (__m64 m, __m64 count)</p> |
| <p>(V)PSRLW:</p> |
| <p>__m128i _mm_srli_epi16 (__m128i m, int count)</p> |
| <p>(V)PSRLW:</p> |
| <p>__m128i _mm_srl_epi16 (__m128i m, __m128i count)</p> |
| <p>VPSRLW:</p> |
| <p>__m256i _mm256_srli_epi16 (__m256i m, int count)</p> |
| <p>VPSRLW:</p> |
| <p>__m256i _mm256_srl_epi16 (__m256i m, __m128i count)</p> |
| <p>PSRLD:</p> |
| <p>__m64 _mm_srli_pi32 (__m64 m, int count)</p> |
| <p>PSRLD:</p> |
| <p>__m64 _mm_srl_pi32 (__m64 m, __m64 count)</p> |
| <p>(V)PSRLD:</p> |
| <p>__m128i _mm_srli_epi32 (__m128i m, int count)</p> |
| <p>(V)PSRLD:</p> |
| <p>__m128i _mm_srl_epi32 (__m128i m, __m128i count)</p> |
| <p>VPSRLD:</p> |
| <p>__m256i _mm256_srli_epi32 (__m256i m, int count)</p> |
| <p>VPSRLD:</p> |
| <p>__m256i _mm256_srl_epi32 (__m256i m, __m128i count)</p> |
| <p>PSRLQ:</p> |
| <p>__m64 _mm_srli_si64 (__m64 m, int count)</p> |
| <p>PSRLQ:</p> |
| <p>__m64 _mm_srl_si64 (__m64 m, __m64 count)</p> |
| <p>(V)PSRLQ:</p> |
| <p>__m128i _mm_srli_epi64 (__m128i m, int count)</p> |
| <p>(V)PSRLQ:</p> |
| <p>__m128i _mm_srl_epi64 (__m128i m, __m128i count)</p> |
| <p>VPSRLQ:</p> |
| <p>__m256i _mm256_srli_epi64 (__m256i m, int count)</p> |
| <p>VPSRLQ:</p> |
| <p>__m256i _mm256_srl_epi64 (__m256i m, __m128i count)</p> |
| <h2>Flags Affected</h2> |
| <p>None.</p> |
| <h2>Numeric Exceptions</h2> |
| <p>None.</p> |
| <h2>Other Exceptions</h2> |
| <p>See Exceptions Type 4 and 7 for non-VEX-encoded instructions; additionally</p> |
| <table class="exception-table"> |
| <tr> |
| <td>#UD</td> |
| <td>If VEX.L = 1.</td></tr></table></body></html> |